Frank Vahid Publications

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C. Gordon, S. Zhao, F. Vahid. Ultra-Lightweight Early Prediction of At-Risk Students in CS1. SIGCSE 2023. conference

F. Vahid, K. Downey, L. Areizaga, A. Pang. Experiences Teaching Coral Before C++ in CS1. SIGCSE 2023. conference   paper

F. Vahid, K. Downey, A. Pang, C. Gordon. Impact of Several Low-Effort Cheating-Reduction Methods in a CS1 Class. SIGCSE 2023. conference   paper

C. L. Gordon, R. Lysecky and F. Vahid, Less Is More: Students Skim Lengthy Online Textbooks. IEEE Transactions on Education, 2022, doi: 10.1109/TE.2022.3199651. paper

C. Gordon, R. Lysecky, F. Vahid. Programming learners struggle as much in Python as in C++ or Java. ASEE 2022. paper

C. Gordon, R. Lysecky, F. Vahid. Understanding and Promoting Earnest Completion in Online Textbooks. ASEE 2022. paper

D. May, F. Vahid. Auto-Awarding Points for Incremental Development in Programming Courses. ASEE 2022. paper

S. Zhao, J. Allen, F. Vahid. Automated Zoom Chat Analysis Including Chat-Based Polls for an Online Introductory Programming Course. ASEE 2022. paper

F. Vahid, T. Givargis, B. Miller. RIOS: A Task Scheduler in Source Code for Teaching and Implementing Concurrent or Real-Time Software. ASEE 2022. paper

N. Alzahrani and F. Vahid. Detecting Possible Cheating In Programming Courses Using Drastic Code Change. ASEE 2022. paper

J. Kelly, A. Edgcomb, J. Bruno, C. Gordon, F. Vahid. Theory to Practice: Reducing Student Attrition in Online Undergraduate Math. Int. Journal of Research in Education and Science (IJRES), Vol 8 No 2, 2022. paper

C. Gordon, R. Lysecky, F. Vahid The shift from static college textbooks to customizable content: A case study at zyBooks 2021 IEEE Frontiers in Education Conference, FIE, Oct 2021. paper

F. Vahid, R. Lysecky, B. Miller, L. Vanderbeek. Coding Trails: Concise Representations of Student Behavior on Programming Tasks. ASEE 2021. paper, DOI 10.18260/1-2--36802.

N. Alzahrani, F. Vahid. Common Logic Errors for Programming Learners: A Three-decade Literature Survey ASEE 2021. paper

N. Alzahrani, F. Vahid. Progression Highlighting for Programming Courses. ASEE 2021. paper

E. Kazakou, A. Edgcomb, Y. Rajasekhar, R. Lysecky, F. Vahid. Randomized, Structured, Auto-graded Homework: Design Philosophy and Engineering Examples. ASEE 2021. paper

C.L. Gordon, R. Lysecky, F. Vahid. The Rise of Program Auto-grading in Introductory CS Courses: A Case Study of zyLabs. ASEE 2021. paper

J. Allen, F. Vahid An Analysis of Using Coral Many Small Programs in CS1 . Journal of Computing Sciences in Colleages, Mar 2021. paper

N. Alzahrani, F. Vahid Progression Highlighting for Programming Courses. Journal of Computing Sciences in Colleages, Mar 2021. paper

J. Allen, F. Vahid. Concise Graphical Representations of Student Effort on Weekly Many Small Programs SIGCSE 2021. paper

F. Vahid, T. Givargis, R. Lysecky. A Pattern Recognition Framework for Embedded Systems ASEE Computers in Education (CoED) journal, Jan-Mar 2020. paper

F. Vahid, A. Edgcomb, R. Lysecky. Using the free Coral language and simulator to simplify first-year programming courses FYEE Annual Conference, 2020. paper

F. Vahid, J. Allen. An online course for freshmen? The evolution of a successful online CS1 course FYEE Annual Conference, 2020. paper

A. Edgcomb, D. McKinney, F. Vahid, R. Lysecky. Improving Pass Rates by Switching from a Passive to an Active Learning Textbook in CS0 ASEE Annual Conference, 2020. paper

J. Allen, F. Vahid. Experiences in Developing a Robust Popular Online CS1 Course for the Past 7 Years ASEE Annual Conference, 2020. DOI 10.18260/1-2--34629 paper

J. Allen, F. Vahid. Analyzing Pivoting Among Weekly Many Small Programs in a CS1 Course ASEE Annual Conference, 2020. paper

J. Allen, F. Vahid. Teaching Coral before C++ in a CS1 Course ASEE Annual Conference, 2020. paper

A. Edgcomb, F. Vahid, R. Lysecky. Coral: An Ultra-Simple Language For Learning to Program ASEE Annual Conference, 2019. paper

J.M. Allen, K. Downey, K. Miller, A. Edgcomb, F. Vahid. Many Small Programs in CS1: Usage Analysis from Multiple Universities ASEE Annual Conference, 2019. paper

N. Sambamurthy, A. Edgcomb, F. Vahid. Animations for Learning: Design Philosophy and Student Usage in Interactive Textbooks ASEE Annual Conference, 2019. paper

Y. Rajasekhar, A. Edgcomb, F. Vahid. Student Usage of Digital Design Interactive Learning Tools in an Online Textbook ASEE Annual Conference, 2019. paper

N. Alzahrani, F. Vahid, A. Edgcomb. Manual Analysis of Homework Coding Errors for Improved Teaching and Help ASEE Annual Conference, 2019. paper

J.M. Allen, F. Vahid, A. Edgcomb, K. Downey, K. Miller. An Analysis of Using Many Small Programs in CS1 ACM SIGCSE (Computer Science Education) conference, 2019. DOI 10.1145/3287324.3287466. paper (search TOC)   (pdf)

M. Amir, F. Vahid, T. Givargis. Switching Predictive Control Using Reconfigurable State-Based Model ACM Transactions on Design Automation of Embedded Systems. paper

J.M. Allen, F. Vahid, K. Downey, A. Edgcomb. Weekly Programs in a CS1 Class: Experiences with Auto-graded Many-small Programs (MSP) ASEE Annual Conference, 2018. (Best paper nominee) paper   (pdf)

N. Alzahrani, F. Vahid, A. Edgcomb, R. Lysecky, S. Lysecky. An Analysis of Common Errors Leading to Excessive Student Struggle on Homework Problems in an Introductory Programming Course ASEE Annual Conference, 2018. paper (pdf)

N. Alzahrani, F. Vahid, A. Edgcomb, R. Lysecky, K. Nguyen. Python versus C++: An analysis of student struggle on small coding exercises in introductory programming courses. ACM SIGCSE (Computer Science Education) conference, 2018. paper

A. Edgcomb, F. Vahid, R. Lysecky, and S. Lysecky. An Analysis of Incorporating Small Coding Exercises as Homework in Introductory Programming Courses, ASEE Annual Conference, 2017. paper

J.M. Allen, F. Vahid, S. Salehain, and A. Edgcomb. Serious games for building skills in computing and engineering, ASEE Annual Conference, 2017. paper

A. Edgcomb, F. Vahid, R. Lysecky, and S. Lysecky. Getting students to earnestly do reading, studying, and homework in an introductory programming class , SIGCSE 2017. pdf

F. Vahid, J.M. Allen, and A. Edgcomb.Web-based games to master core skills in introductory college mathematics, Joint Mathematics Meeting, 2017. (Abstract only). pdf

J. Yuen, A. Edgcomb, and F. Vahid. Will Students Earnestly Attempt Learning Questions if Answers are Viewable?, ASEE Annual Conference, 2016. paper

A. Edgcomb and F. Vahid. Simplifying a Course to Reduce Student Stress so Students Can Focus Again on Learning, ASEE Annual Conference, 2016. paper

F. Vahid, S. Lysecky, and A. Edgcomb. Introduction to Computing Technology: New Interactive Animated Web-Based Learning Content, ASEE Annual Conference, 2016. paper

F. Vahid, A. Edgcomb, S. Lysecky, and R. Lysecky. New Web-Based Interactive Learning Material for Digital Design, ASEE Annual Conference, 2016. paper

F. Vahid, A. Edgcomb, B. Miller, and T. Givargis. Learning Materials for Introductory Embedded Systems Programming using a Model-Based Discipline, ASEE Annual Conference, 2016. paper

F. Vahid and A. Edgcomb. New College-Level Interactive STEM Learning Material: Findings and Directions, AAAS NSF Symposium on EnFUSE (Envisioning the Future of Undergraduate STEM Education: Research and Practice), 2016.

F. Vahid, D. de Haas, S. Strawn, A. Edgcomb, S. Lysecky, R. Lysecky. A Continual Improvement Paradigm for Modern Online Textbooks. Int. Conf. of Education, Research and Innovation (ICERI), Spain, Nov. 2015.

A. Edgcomb, D. De Haas, R. Lysecky, F. Vahid. Student usage and behavioral patterns with online interactive textbook materials. Int. Conf. of Education, Research and Innovation (ICERI), Spain, Nov. 2015.

A. Edgcomb, F. Vahid. How Many Points Should Be Awarded for Interactive Textbook Reading Assignments? Proc. of Frontiers in Education conference (FIE), El Paso, Oct. 2015. paper

A. Edgcomb, F. Vahid, R. Lysecky, Students Learn More with Less Text that Covers the Same Core Topics Proc. of Frontiers in Education conference (FIE), El Paso, Oct. 2015. paper

A. Edgcomb, F. Vahid, R. Lysecky, A. Knoesen, R. Amirtharajah, and M.L. Dorf. Student Performance Improvement using Interactive Textbooks: A Three-University Cross-Semester Analysis, Proc. of ASEE Annual Conference, Seattle, June 2015. (Best paper award). DOI 10.18260/p.24760. paper

A. Edgcomb, J. Yuen, F. Vahid. Experiments in Student Crowdsourcing of Practice Question and Animation Creation, Proc. of ASEE Annual Conference, Seattle, June 2015. paper

V. Gunes, S. Peter, T. Givargis, F. Vahid. A Survey on Concepts, Applications, and Challenges in Cyber-Physical Systems. KSII Transactions on Internet and Information Systems, vol. 8, no. 12, Dec. 2014. paper

B. Miller, F. Vahid, T. Givargis, P. Brisk. Graph-Based Approaches to Placement of Processing Element Networks on FPGAs for Physical Model Simulation. ACM Transactions on Reconfigurable Technology and Systems. 2014, Issue 10. paper

A. Edgcomb, F. Vahid. Effectiveness of Online Textbooks vs. Interactive Web-Native Content American Society of Engineering Educators Annual Conference, ASEE 2014, Best paper award. DOI 10.18260/1-2--20351 paper

A. Edgcomb, F. Vahid. Accurate and Efficient Algorithms that Adapt to Privacy-Enhanced Video for Improved Assistive Monitoring ACM Transactions on Management Information Systems (TMIS): Special Issue on Informatics for Smart Health and Wellbeing, 2013. pdf

B. Miller, F. Vahid, T. Givargis. Exploration with upgradeable models using statistical methods for physical model emulation IEEE/ACM Design Automation Conference (DAC'13), June 2013. paper

S. Peter, F. Vahid, T. Givargis. A Ball Goes to School -- Our Experiences from a CPS Design Experiment. Workshop on Cyber-Physical Systems Education (CPS-Ed) at Cyber Physical Systems Week (CPSWeek), pp. 1-4, Philadelphia, April 2013.

B. Miller, F. Vahid, T. Givargis. Embedding-based placement of processing element networks on FPGAs for physical model simulation. ACM Int. Symp. on FPGAs, Feb 2013, pp 181-190. paper

C. Huang, B. Miller, F. Vahid, T. Givargis. Synthesis of networks of custom processing elements for real-time physical system emulation. ACM Trans. on Design Automation of Electronic Systems (TODAES), Vol 18, Issue 2, April 2013, 21 pages. paper

A. Edgcomb, F. Vahid. Automated In-Home Assistive Monitoring with Privacy-Enhanced Video. IEEE International Conference on Healthcare Informatics (ICHI), 2013. paper

A. Edgcomb, F. Vahid. Estimating Daily Energy Expenditure from Video for Assistive Monitoring. IEEE International Conference on Healthcare Informatics (ICHI), 2013. paper

A. Edgcomb, F. Vahid. Interactive Web Activities for Online STEM Learning Materials. American Society for Engineering Education Pacific Southwest Section Conference, 2013.

T.S. Chou, C. Huang, B. Miller, T. Givargis, F. Vahid. An Efficient Compression Scheme for Checkpointing of FPGA-Based Digital Mockups. IEEE/ACM Asian and South Pacific Design Automation Conference (ASP-DAC), Japan, January 2013. paper

A. Edgcomb, F. Vahid. Privacy Perception and Fall Detection Accuracy for In- Home Video Assistive Monitoring with Privacy Enhancements. ACM SIGHIT (Special Interest Group on Health Informatics) Record, 2012. pdf

C. Huang, B. Miller, F. Vahid, T. Givargis. Synthesis of Custom Networks of Heterogeneous Processing Elements for Complex Physical System Emulation. IEEE/ACM Conference on Hardware/Software Codesign and System Synthesis (CODES/ISSS, part of ESWEEK), Finland, Oct 2012. paper

B. Miller, F. Vahid, T. Givargis. RIOS: A Lightweight Task Scheduler for Embedded Systems. Workshop on Embedded Systems Education (WESE, part of ESWEEK), Finland, Oct 2012. pdf

A. Edgcomb, F. Vahid. Automated Fall Detection on Privacy-Enhanced Video. Engineering in Medicine and Biology Conference (EMBC), San Diego, August 2012.

B. Miller, F. Vahid, T. Givargis. MEDS: Mockup Electronic Data Sheets for Automated Testing of Cyber-Physical Systems Using Digital Mockups. Design Automation and Test in Europe, March 2012.

B. Miller, F. Vahid, T. Givargis. Digital Mockups for the Testing of a Medical Ventilator, ACM SIGHIT Symposium on International Health Informatics (IHI), 2012, pp. 859-862. pdf

A. Edgcomb, F. Vahid. MNFL: The Monitoring and Notification Flow Language for Assistive Monitoring, ACM SIGHIT International Health Informatics Symposium (IHI), 2012, pp. 191-200. pdf

C. Huang, F. Vahid, and T. Givargis. A Custom FPGA Processor for Physical Model Ordinary Differential Equation Solving, IEEE Embedded Systems Letters, September 2011, pp. 113-116. pdf

A. Edgcomb, F. Vahid. Feature Extractors: Flexible Integration of Cameras and Sensors for End-User Programming of Assistive Monitoring Systems, Wireless Health, 2011, 2 pages. pdf

G. Stitt and F. Vahid. Thread Warping: Dynamic and Transparent Synthesis of Thread Accelerators ACM Trans. on Design Automation of Electronic Systems (TODAES), Vol 16, Issue 3, June 2011, 21 pages. pdf


A. Becker, S. Sirowy, F. Vahid. Just-in-Time Compilation for FPGA Processor Cores IEEE Electronic System Level Synthesis Conf. (ESLsyn), June 2011. pdf   ppt  


B. Miller, F. Vahid, T. Givargis. Application-Specific Codesign Platform Generation for Digital Mockups in Cyber-Physical Systems IEEE Electronic System Level Synthesis Conf. (ESLsyn), June 2011, pp 1-6. pdf   ppt  


C. Huang, F. Vahid Scalable Object Detection Accelerators on FPGAs Using Custom Design Space Exploration IEEE Symposium on Application Specific Processors (SASP), June 2011, pp 115-121. pdf   ppt  


S. Sirowy, C. Huang, and F. Vahid. Online SystemC Emulation Acceleration. IEEE/ACM Design Automation Conference, June 2010. pdf


C. Huang and F. Vahid. Server-Side Coprocessor Updating for Mobile Devices with FPGAs . ACM Int. Symp. on FPGAs, Feb 2010, pp 125-134. pdf


S. Sirowy, T. Givargis, F. Vahid. Digitally-Bypassed Transducers: Interfacing Digital Mockups to Real-Time Medical Equipment. Int. Conf. of the IEEE Engineering in Medicine and Biology Society (EMBC), Sept 2009. pdf   ppt  


S. Sirowy, C. Huang, and F. Vahid. Dynamic Acceleration Management for SystemC Emulation. Adaptive and Reconfigurable Embedded Systems (APRES, part of ESWEEK), Oct 2009, 4 pages. pdf  


S. Sirowy, B. Miller, and F. Vahid. Portable SystemC-on-a-Chip. IEEE/ACM Conference on Hardware/Software Codesign and System Synthesis (CODES/ISSS, part of ESWEEK), Oct 2009, pp 21-30. pdf  


C. Huang, F. Vahid. Transmuting coprocessors: Dynamic loading of FPGA coprocessors. IEEE/ACM Design Automation Conference, July 2009, pp 848-851. pdf


F. Vahid. What is Hardware/Software Partitioning? ACM SIGDA Newsletter, June 2009. txt  

D. Sheldon, F. Vahid. Making Good Points: Application-Specific Pareto-Point Generation for Design Space Exploration using Statistical Methods. ACM Symp. on FPGAs, Feb 2009, pp 123-132. pdf   ppt  


R. Lysecky, F. Vahid. Design and Implementation of a MicroBlaze-based Warp Processor. ACM Transactions on Embedded Computing Systems (TECS), Vol 8, Issue 3, April 2009, 22 pages. pdf  


S. Sirowy, D. Sheldon, T. Givargis, and F. Vahid. Virtual Microcontrollers ACM SIGBED Review, Vol. 6., Issue 1, 2009, 8 pages. pdf  


S. Lysecky and F. Vahid. Enabling Non-Expert Construction of Basic Sensor-Based Systems ACM Trans. on Computer-Human Interaction (TOCHI), Vol 16, Issue 1, Apr 2009, 28 pages. pdf  


A. Gordon-Ross, F. Vahid, and N. Dutt. Fast Configurable-Cache Tuning with a Unified Second-Level Cache . IEEE Transactions on VLSI (TVLSI), Vol 17, Issue 1, Jan 2009. pdf  


S. Sirowy, D. Sheldon, T. Givargis, and F. Vahid. Virtual Microcontrollers Int. Wkshp. on Embedded Systems Education, (WESE), Oct 2008, 6 pages. pdf (to appear)


F. Vahid and T. Givargis. Timing is Everything -- Embedded Systems Demand Teaching of Structured Time-Oriented Programming . Int. Wkshp. on Embedded Systems Education, (WESE), Oct 2008. pdf  

C. Huang, D. Sheldon, and F. Vahid. Dynamic Tuning of Configurable Architectures: The AWW Online Algorithm . IEEE/ACM Int. Conf. on Hardware/Software Codesign and System Synthesis, (CODES/ISSS), Oct 2008. pdf   Data and Tools  


D. Sheldon and F. Vahid. Don't Forget Memories: A Case Study Redesigning a Pattern Counting ASIC Circuit for FPGAs. IEEE/ACM Int. Conf. on Hardware/Software Codesign and System Synthesis, (CODES/ISSS), Oct 2008. pdf  


F. Vahid and T. Givargis. Highly-Cited Ideas in System Codesign and Synthesis. IEEE/ACM Int. Conf. on Hardware/Software Codesign and System Synthesis, (CODES/ISSS), Oct 2008. pdf   ppt   data (xls) (posted for a limited time) 


C. Huang and F. Vahid. Dynamic Coprocessor Management for FPGA-Enhanced Compute Platforms. IEEE/ACM Int. Conf. on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), Oct 2008. pdf   Data and Tools  


F. Vahid, G. Stitt, and R. Lysecky. Warp Processing: Dynamic Translation of Binaries to FPGA Circuits . IEEE Computer, Vol. 41, No. 7, July 2008, pp. 40-46. pdf  


P. Viana, A. Gordon-Ross, E. Barros, F. Vahid. A Table-Based Method for Single-Pass Cache Optimization . ACM Great Lakes Symposium on VLSI, May 2008, pp. 71-76. pdf  


S. Sirowy, G. Stitt, and F. Vahid. C is for Circuits: Capturing FPGA Circuits as Sequential Code for Portability. ACM Int. Symp. on FPGAs, 2008, pp. 117-126. pdf  


F. Vahid and G. Stitt. Hardware/Software Partitioning . Chapter 26 in S. Hauck, A. DeHon (editors), Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation", Morgan Kaufmann/Elsevier, 2008. pdf not available  


F. Vahid. It's Time to Stop Calling Circuits Hardware. IEEE Computer Magazine, September 2007, Vol 40, Issue 9, pp. 106-108 . pdf  


G. Stitt and F. Vahid. Thread Warping: A Framework for Dynamic Synthesis of Thread Accelerators. Int. Conf. on Hardware/Software Codesign and System Synthesis (CODES/ISSS), 2007, pp. 93-98. pdf   ppt  


A. Gordon-Ross and F. Vahid. A Self-Tuning Configurable Cache. Design Automation Conference (DAC), 2007, pp. 234-237. pdf   ppt  


K. Schleupen, S. Lekuch, R. Mannion, Z. Guo, W. Najjar, and F. Vahid. Dynamic Partial FPGA Reconfiguration in a Prototype Microprocessor System . (FPL), 2007, pp. 533-536. pdf (to appear)   ppt (to appear)  


G. Stitt and F. Vahid. Binary Synthesis. ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 12 No. 3, Aug 2007. pdf  

S. Sirowy and F. Vahid. Integrated Coupling and Clock Frequency Assignment of Accelerators During Hardware/Software Partitioning Assignment. International Embedded Systems Symposium (IESS), 2007, pp. 145-154. pdf   ppt  


D. Sheldon, F. Vahid and S. Lonardi. Soft-Core Processor Customization Using the Design of Experiments Paradigm. IEEE/ACM Design Automation and Test in Europe (DATE), 2007, pp. 821-826. pdf   ppt  


A. Gordon-Ross, P. Viana, F. Vahid, W. Najjar, E. Barros. A One-Shot Configurable-Cache Tuner for Improved Energy and Performance. IEEE/ACM Design Automation and Test in Europe (DATE), 2007, pp. 755-760. pdf   ppt  


S. Sirowy, Y. Wu, S Lonardi and F. Vahid. Two Level Microprocessor-Accelerator Partitioning. IEEE/ACM Design Automation and Test in Europe (DATE), 2007, pp. 313-318. pdf   ppt  


S. Sirowy, Y. Wu, S Lonardi and F. Vahid. Clock-Frequency Partitioning for Multiple Clock Domains Systems-on-a-Chip. IEEE/ACM Design Automation and Test in Europe (DATE), 2007, pp. 397-402. pdf   ppt  


D. Sheldon, R. Kumar, F. Vahid, D.M. Tullsen, R. Lysecky
Conjoining Soft-Core FPGA Processors IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2006, pp. 694-701. pdf   ppt  


G. Stitt, F. Vahid, W. Najjar
A Code Refinement Methodology for Performance-Improved Synthesis from C IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2006, pp. 716-723. pdf   ppt  


D. Sheldon, R. Kumar, R. Lysecky, F. Vahid, D.M. Tullsen,
Application-Specific Customization of Parameterized FPGA Soft-Core Processors IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2006, pp. 261-268. pdf   ppt  


S. Lysecky, F. Vahid.
Automated Application-Specific Tuning of Parameterized Sensor-Based Embedded System Building Blocks Int. Conf. on Ubiquitous Computing (UbiComp), Sep. 2006, pp. 507-524. pdf   ppt  


S. Lysecky, F. Vahid.
Automated Generation of Basic Custom Sensor-Based Embedded Computing Systems Guided by End-User Optimization Criteria Int. Conf. on Ubiquitous Computing (UbiComp), Sep. 2006, pp. 69-86. pdf   ppt  


R. Lysecky, G. Stitt, F. Vahid.
Warp Processors. ACM Transactions on Design Automation of Electronic Systems (TODAES), July 2006, pp. 659-681. pdf   Listed in top-10 most-cited TODAES articles of all time, top-5 since 2000 (as of Nov 2016)


P. Viana, A. Gordon-Ross, E. Keogh, E. Barros, F. Vahid.
Configurable Cache Subsetting for Fast Cache Tuning. IEEE/ACM Design Automation Conference (DAC), July 2006, pp. 695 - 700. pdf  


G. Stitt, F. Vahid
New Decompilation Techniques for Binary-level Co-processor Generation IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2005, pp. 547-554. pdf  


A. Gordon-Ross, F. Vahid, N. Dutt.
Fast Configurable-Cache Tuning with a Unified Second-Level Cache International Symposium on Low-Power Electronics and Design (ISLPED), Aug. 2005, pp. 323-326. pdf  


G. Stitt, F. Vahid, G. McGregor, B. Einloth.
Hardware/Software Partitioning of Software Binaries: A Case Study of H.264 Decode International Conference on Hardware/Software Codesign and System Synthesis (CODES/ISSS), Sep. 2005, pp. 285-290. pdf  
Shows that binary-level partitioning and synthesis of a real highly-optimized h264 video decoder application is competitive with source (C) level partitioning/synthesis. Also introduces several simple C coding guidelines that greatly improve synthesis results.

A. Gordon-Ross and F. Vahid.
Frequent Loop Detection Using Efficient Non-Intrusive On-Chip Hardware. IEEE Transactions on Computers, Special Issue-Embedded Systems, Microarchitecture, and Compilation Techniques in Memory of B. Ramakrishna (Bob) Rau, Oct. 2005, Vol. 54, Issue 10, pp 1203-1215. pdf  
Describes extensive studies resulting in lean profiler hardware that effectively finds addresses corresponding to frequent loops in an executing software binary.

S. Cotterell and F. Vahid.
Usability of State Based Boolean eBlocks. 11th International Conference on Human-Computer Interaction (HCII), 2005, pp. pdf  
Four basic state-based blocks -- prolonger, tripper, toggle, and pulse generator -- are understandable by novice users and can be connected to define a good range of desired sensor-system behavior.

R. Lysecky, F. Vahid and S. Tan.
A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation. IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), 2005, pp. 57-62. pdf  
Describes an FPGA routing approach that is lean in terms of runtime and memory, running three times faster while using over 15 times less memory than a popular router, yet creating a critical path that is only 30% longer on average and about equal for very large circuits compared to that other router. Our approach, ROCR (Riverside On-Chip Router), can be useful for methods requiring just-in-time FPGA compilation, like our warp processing method, and future methods using a standard FPGA binary.

S. Cotterell and F. Vahid. A Logic Block Enabling Logic Configuration by Non-Experts in Sensor Networks. Conference on Human Factors in Computing (CHI), 2005, pp. 1925 - 1928. pdf  
Describes attempts to build a logic block that non-experts could configure to compute particular sensor conditions (e.g., motion and no light). Shows that a truth table based block is too complicating to non-experts, but a sentence based block exhibits high success, though being less general. A truth table using color and presented in a sentence format also exhibits reasonable success while being more general.

C. Zhang, F. Vahid, J. Yang, and W. Najjar.
A Way-Halting Cache for Low-Energy High-Performance Systems. ACM Transactions on Architecture and Code Optimization (TACO), Vol. 2, No. 1, March 2005, pp 34-54. pdf  
Describes a cache design that separates the four low-order tags bits into its own fully-associative memory (a halt-tag array). Concurrently with address decoding, the halt-tag array determines mismatches in the low-order four tag bits (of all the tags). A mismatch masks out the decode line, halting further tag and data access. A way-halting cache yields 55% memory access energy savings on average, with no performance overhead.


A. Gordon-Ross, F. Vahid, N. Dutt.
A First Look at the Interplay of Code Reordering and Configurable Caches. Great Lakes Symposium on VLSI (GLSVLSI), April 2005, pp. 416-421. pdf  
Shows that a configurable cache dominates over compiler-based code reordering with respect to tuning an application to a cache for power and performance improvements. Yet, combining the two methods does result in a smaller overall cache size, 13% on average and up to 89%.


S. Cotterell, R. Mannion, F. Vahid, H. Hsieh.
eBlocks - An Enabling Technology for Basic Sensor Based Systems IPSN Track on Sensor Platform, Tools and Design Methods for Networked Embedded Systems (SPOTS), April 2005. pdf  
Describes how physical eBlock prototypes and a graphical eBlock simulation tool were used by hundreds of users during the development and refinement of eBlock sensor network nodes


C. Zhang, F. Vahid and W. Najjar.
A Highly Configurable Cache for Low Energy Embedded Systems. ACM Transactions on Embedded Computing Systems (TECS), Vol. 4, Issue 2, May 2005, pp. 363-387. pdf  
Describes a cache whose total size, associativity, and line size can be configured just by setting a few bits in a configuration register. Provides experimental results demonstrating that tuning the configuration to a particular software application's needs reduces memory access energy by over 40% on average across a large set of benchmarks.

R. Lysecky and F. Vahid.
A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning. Design Automation and Test in Europe (DATE), March 2005, pp. 18-23. pdf  
ppt  
Highlights speedup and energy results of implementing warp processing, which dynamically and transparently remaps software kernels to FPGA using on-chip synthesis tools, for software running on a Xilinx MicroBlaze soft-core processor. Results show competitive performance and energy compared to software on regular "hard core" embedded microprocessors, thus making soft-cores on FPGA even more attractive beyond just their flexibility of putting different numbers of cores and custom circuitry on a single chip.

G. Stitt and F. Vahid.
A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms. Design Automation and Test in Europe (DATE), March 2005, pp. 396-397. pdf  
Utilizing advanced decompilation techniques enables synthesis of hardware from binaries to recover nearly all high-level constructs that existed in the source code, even for different compiler optimization levels.

R. Mannion, H. Hsieh, S. Cotterell, F. Vahid.
System Synthesis for Networks of Programmable Blocks. Design Automation and Test in Europe (DATE), March 2005, pp. 888-893. pdf   ppt  
Describes techniques to automatically convert a network of pre-defined eBlocks into a minimal number of programmable eBlocks, while also generating code for those blocks.

G. Stitt, Z. Guo, F. Vahid, and W. Najjar.
Techniques for Synthesizing Binaries to an Advanced Register/Memory Structure. ACM/SIGDA Symp. on Field Programmable Gate Arrays (FPGA), Feb. 2005, pp. 118-124. pdf  
Advanced decompilation methods can make synthesizing FPGA hardware from software binaries competitive with synthesizing directly from C-level source code, even when utilizing an advanced memory structure (smart buffer) requiring knowledge of loops and arrays. Synthesis from binaries provides numerous advantages of language independence, tool independence, portability, and support of legacy code.

S. Cotterell, K. Downey, and F. Vahid.
Applications and Experiments with eBlocks -- Electronic Blocks for Basic Sensor-Based Systems. IEEE Sensor and Ad Hoc Communications and Networks (SECON), Oct 2004. pdf   ppt  
Describes common applications that can be built just by connecting eBlocks together, enabling people without programming experience to build useful sensor-based systems. Summarizes experiences with hundreds of users, showing success rates even when utilizing logic and state based blocks.

C. Zhang, F. Vahid, J. Yang and W. Najjar.
A Way-Halting Cache for Low-Energy High-Performance Systems International Symposium on Low-Power Electronics and Design (ISLPED), Aug 2004, pp. 126-131. pdf  
Describes a cache whose tag comparison logic includes a small and fast fully-associative memory that quickly detects a mismatch in a particular cache way, and then halts further tag and data access of that way, thus saving power.

R. Lysecky, F. Vahid, and S. Tan.
Dynamic FPGA Routing for Just-in-Time FPGA Compilation . Design Automation Conference (DAC), June 2004, pp. 954-959. pdf   ppt  
Describes an FPGA routing heuristic suitable for execution on-chip, to support Just-in-Time compilation for FPGAs.

A. Gordon-Ross, C. Zhang, F. Vahid. N. Dutt.
Tuning caches to applications for low-energy embedded systems. Chapter 6 in Ultra Low-Power Electronics and Design - Kluwer Academic Pub, June 2004. pdf  


C. Zhang, F. Vahid and R. Lysecky. A Self-Tuning Cache Architecture for Embedded Systems. ACM Transactions on Embedded Computing Systems (TECS), Vol. 3., Issue 2, May 2004, pp. 407-425. pdf   Describes a configurable cache that monitors its own hit rate, and automatically reconfigures the cache's number of ways (associativity), line size and total size to reduce power and/or improve performance, using an efficient heuristic that not only prunes the configuration search space but also avoids cache flushes during the search.

Z. Guo, W. Najjar, F. Vahid and K. Visssers.
A Quantitative Analysis of the Speedup Factors of FPGAs over Processors. ACM/IEEE International Symposium on Field-Programmable Gate Arrays, Feb. 2004. pdf  


R. Lysecky and F. Vahid.
A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning. Design Automation and Test in Europe Conference (DATE), February 2004, pp. 480-485. pdf   ppt
Describes a simple configurable logic (FPGA) fabric and surrounding architecture specifically intended to support dynamic hardware/software partitioning -- meaning on-chip CAD tools must be able to quickly map a netlist to the fabric.

A. Gordon-Ross, F. Vahid and N. Dutt. Automatic Tuning of Two-Level Caches to Embedded Applications. Design Automation and Test in Europe Conference (DATE), February 2004, pp. 208-213. pdf   ppt
Describes efficient heuristics for tuning a two-level cache to a particular application, obtaining near-optimal memory-access energy savings of 53%-55% through such tuning, while exploring a mere 6% of the total configuration space.

C. Zhang and F. Vahid.
Using a Victim Buffer in an Application-Specific Memory Hierarchy Design Automation and Test in Europe Conference (DATE), February 2004, pp. 220-225. pdf   ppt
Adding to a cache a configurable victim buffer, which can be turned on or off, improves memory-access energy of an application by up to 43%. Such savings occur even if the cache itself is configurable. Making the buffer configurable enables us to shut off the buffer for some applications that otherwise would suffer increased energy and performance penalties of up to 4%.

C. Zhang, F. Vahid and R. Lysecky.
A Self-Tuning Cache Architecture for Embedded Systems. Design Automation and Test in Europe Conference (DATE), February 2004, pp. 142-147. pdf   ppt
Describes a configurable cache that can tune its total size, associativity, and line size to an executing application. The search heuristic is carefully designed to avoid flushing. The cache transparently reduces memory-access related energy by 45%-55% on average, and by as much as 97% for particular applications.

C. Zhang, J. Yang and F. Vahid.
Low Static-Power Frequent-Value Data Caches. Design Automation and Test in Europe Conference (DATE), February 2004, pp. 214-219. pdf   ppt
Improves upon Yang/Gupta's previous frequent value cache, by eliminating performance overhead, and saving static power in addition to dynamic power, using circuit level design improvements. A frequent value cache encodes commonly-occurring data values into just a few bits, shutting down the remaining bit storage cells. 33% static energy savings are obtained.

G. Stitt, F. Vahid, S. Nemetebaksh.
Energy Savings and Speedups from Partitioning Critical Software Loops to Hardware in Embedded Systems. IEEE Transactions on Embedded Computer Systems, January 2004. pdf
Partitioning a program's kernels to FPGA hardware can reduce overall system energy.

C. Zhang, F. Vahid, J. Yang, W. Najjar.
A Way-Halting Cache for Low-Energy High-Performance Systems IEEE Computer Architecture Letters, Vol. 2, Sep. 2003. pdf
The first four bits of a cache's tags are stored in a fast efficient CAM and accessed concurrently with set decoding -- if those four bits mismatch for the decoded set, the full tag comparisons and data array accesses are "halted," thus saving power, with no performance overhead (unlike other power-saving caches).

A. Gordon-Ross and F. Vahid.
Frequent Loop Detection Using Efficient Non-Intrusive On-Chip Hardware. ACM/IEEE Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), 2003, pp. 117-124. pdf
Describes efficient non-intrusive hardware for detecting the most frequent loops in an executing binary, and the relative frequencies of those loops.

S. Cotterell, F. Vahid, W. Najjar and H. Hsieh.
First Results with eBlocks: Embedded Systems Building Blocks. ACM/IEEE ISSS/CODES conference, 2003, pp. 168-175. pdf
Describes embedded system building blocks that people with no training can connect together to build simple but useful systems.

R. Lysecky and F. Vahid.
A Codesigned On-Chip Logic Minimizer. ACM/IEEE ISSS/CODES conference, 2003, pp. 109-113. pdf
Hardware/software partitioning of an on-chip logic minimizer results in 8x speedup and 60% energy savings, improving the usefulness of on-chip logic minimization in a variety of applications.

A. Gordon-Ross, S. Cotterell, and F. Vahid.
Tiny Instruction Caches For Low Power Embedded Systems. ACM Transactions on Embedded Computing Systems, Vol. 2, Issue 4, Nov. 2003, pp. 449-481. pdf
Putting a very small (e.g., 128 word) loop cache in front of L1 instruction cache can greatly reduce power, with no performance overhead.

D.C. Suresh, W.A. Najjar, F. Vahid, J.R. Villarreal, G. Stitt.
Profiling tools for hardware/software partitioning of embedded applications. Languages, Compilers and Tools for Embedded Systems (LCTES), 2003, pp. 189-198. pdf


C. Zhang, F. Vahid and W. Najjar.
A Highly-Configurable Cache Architecture For Embedded Systems. International Symposium on Computer Architecture, 2003, pp. 136-146. pdf
A cache with whose number of ways and total size can be tuned to a particular program yields big energy savings with almost no performance overhead.

C. Zhang and F. Vahid.
Cache Configuration Exploration on Prototyping Platforms. Rapid System Prototyping, 2003, pp. 164-171. pdf
Methods to automatically tune a configurable cache to a particular software application.

G. Stitt, R. Lysecky and F. Vahid.
Dynamic Hardware/Software Partitioning: A First Approach. Design Automation Conference, 2003, pp. 250-255. pdf
Dynamically partitioning an executing software application onto on-chip FPGA is not only possible, but quite effective.

R. Lysecky and F. Vahid.
On-Chip Logic Minimization. Design Automation Conference, 2003, 334-337. pdf
Executing a lean form of logic minimization on-chip is feasible and has several immediate applications in networking.

F. Vahid.
Embedded System Design: UCR's Undergraduate Three- Course Sequence Microelectronics Systems Engineering (MSE) conference, 2003. pdf
Summarizes UCR's successful 3-course sequence on embedded system design, based on the new ESD book (see above) that emphasizes a unified view of hardware and software.

F. Vahid.
The Softening of Hardware IEEE Computer, April 2003, pp. 27-34. pdf
A new perspective on hardware becoming much more like software, due in part to configurable logic, and in part to hardware being created today by compiling high-level languages.

F. Vahid, R. Lysecky, C. Zhang and G. Stitt.
Highly Configurable Platforms for Embedded Computing Systems Microelectronics Journal, Elsevier Publishers, Volume 34, Issue 11, November 2003, Pages 1025-1029. pdf
The case for creating platform chips with much configurability, including on-chip FPGA, configurable cache, etc.
Online version


F. Vahid.
Making the Best of those Extra Transistors. IEEE Design and Test of Computers, Jan/Feb 2003, pg. 96. pdf
An argument for new uses of the abundant transistors on modern chips.

C. Zhang, F. Vahid, W. Najjar.
Energy Benefits of a Configurable Line Size Cache for Embedded Systems. IEEE Computer Society Annual Symposium on VLSI, Feb. 2003, pp. 87-91. pdf
Creating a cache with a line size that can be configured to 16, 32 or 64 bytes results in suprisingly large energy savings.

T. Givargis and F. Vahid.
Platune: A Tuning Framework for System-on-a-Chip Platforms. IEEE Transactions on Computer Aided Design, Vol. 21, No. 11, Nov. 2002, pp. 1317-1327. pdf
Platune tunes an architecture to an application by rapidly exploring the huge configuration space of configurable caches, buses, voltage levels, and many any other configurable architectural parameters.

T. Givargis, F. Vahid and J. Henkel.
Instruction-based System-level Power Evaluation of System-on-a-chip Peripheral Cores. IEEE Transactions on VLSI, pp. 856-863, Vol 10, No 6, Dec. 2002. pdf
We break peripheral behavior into "instructions" and back-annotate those instructions with low-level power data, yielding fast and accurate system-level power estimations.

F. Vahid, T. Givargis and S. Cotterell.
Power Estimator Development for Embedded System Memory Tuning. Journal of Circuits, Systems and Computers, vol. 11, no. 5, pp. 459-476, October 2002. pdf not avail
We describe three increasingly accurate methods for estimating power of a memory hierarchy.

F. Vahid.
Partitioning Sequential Programs for CAD using a Three-Step Approach. ACM Transactions on Design Automation of Electronic Systems, Vol 7, Issue 3, pp 413-429, July 2002. pdf


G. Stitt and F. Vahid.
The Energy Advantages of Microprocessor Platforms with On-Chip Configurable Logic. IEEE Design and Test of Computers, November/December 2002, pp. 36-43.    pdf


T. Givargis, F. Vahid and J. Henkel.
System-level Exploration for Pareto-optimal Configurations in Parameterized System-on-a-chip. IEEE Transactions on VLSI Systems, Vol. 10, Issue 4, Dec. 2002, pp. 416-422.    pdf


J. Villarreal, D. Suresh, G. Stitt, F. Vahid and W. Najjar.
Improving Software Performance with Configurable Logic. Kluwer Journal on Design Automation of Embedded Systems, November 2002, Volume 7, Issue 4, pp. 325-339.    pdf


G. Stitt and F. Vahid.
Hardware/Software Partitioning of Software Binaries. IEEE/ACM International Conference on Computer Aided Design, November 2002, pp. 164-170.    pdf


S. Cotterell and F. Vahid.
Synthesis of Customized Loop Caches for Core-Based Embedded Systems. IEEE/ACM International Conference on Computer Aided Design, November 2002, pp. 655-662.    pdf


S. Cotterell and F. Vahid.
Tuning of Loop Cache Architectures to Programs in Embedded System Design. IEEE/ACM International Symposium on System Synthesis, October 2002, pp. 8-13.    pdf    ppt slides


A. Gordon-Ross and F. Vahid.
Dynamic Loop Caching Meets Preloaded Loop Caching -- A Hybrid Approach. International Conference on Computer Design, September 2002, pp. 446-449.    pdf    ppt slides


T. Givargis and F. Vahid.
Tuning of Cache Ways and Voltage for Low-Energy Embedded System Platforms. Kluwer Journal on Design Automation of Embedded Systems, vol. 7, issue 1-2, pp. 35-51, September 2002.    pdf


R. Lysecky, S. Cotterell and F. Vahid.
A Fast On-Chip Profiler Memory IEEE/ACM Design Automation Conference, June 2002, pp. 28-33.    pdf


B. Grattan, G. Stitt and F. Vahid.
Codesign-Extended Applications. IEEE/ACM International Symposium on Hardware/Software Codesign, Estes Park, May 2002, pp. 1-6.    pdf    ppt slides


C. Zhang and F. Vahid.
A Power-Configurable Bus for Embedded Systems. IEEE International Symposium on Circuits and Systems, Scottsdale, May 2002, pp.V-809-812.    pdf


G. Stitt, B. Grattan, J. Villarreal and F. Vahid.
Using On-Chip Configurable Logic to Reduce Embedded System Software Energy. IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa Valley, April 2002, pp. 143-151.    pdf


G. Stitt and F. Vahid.
Propagating Constants Past Software to Hardware Peripherals in Fixed-Application Embedded Systems. In book "Compilers and operating systems for low power," editors L. Benini, M. Kandemir, J. Ramanujam, Kluwer Academic Publishers, 2003, Chapter 7, pp. 115-136.    pdf


A. Gordon-Ross, S. Cotterell and F. Vahid.
Exploiting Fixed Programs in Embedded Systems: A Loop Cache Example. IEEE Computer Architecture Letters, Vol 1, January 2002.    pdf


R. Lysecky and F. Vahid.
Prefetching for Improved Bus Wrapper Performance in Cores. ACM Transactions on Design Automation of Electronic Systems, Vol. 7, No. 1, pp. 58-90, January 2002.    pdf


F. Vahid, R. Patel and G. Stitt.
Propagating Constants Past Software to Hardware Peripherals in Fixed-Application Embedded Systems.
Special Issue of ACM SIGARCH Newsletter, Dec. 2001.    pdf    html (of COLP paper)    slides
Selected for special issue from earlier version of paper in Compilers and Operating Systems for Low Power (COLP'01).
Describes the size and power advantages of recognizing that software-configurable control registers in peripherals may never change after being initialized, if the software itself never changes (as is common in embedded systems).

T. Givargis and F. Vahid and J. Henkel.
System-level Exploration for Pareto-optimal Configurations in Parameterized Systems-on-a-chip. International Conference on Computer Aided Design, Nov 2001, pp. 25-30.    pdf    html    slides
Provides a technique for efficiently exploring the configuration space of a parameterized system-on-a-chip (SOC) architecture to find all Pareto-optimal configurations. These configurations represent the range of meaningful power and performance tradeoffs that are obtainable by adjusting parameter values for a fixed application mapped onto the SOC architecture. Our approach extensively prunes the potentially large configuration space by taking advantage of parameter dependencies. We have successfully incorporated our technique into the parameterized SOC tuning environment (Platune) and applied it to a number of applications.

T. Givargis, F. Vahid and J. Henkel.
Evaluating Power Consumption of Parameterized Cache and Bus Architectures in System-on-a-Chip Designs. IEEE Transactions on VLSI, Vol 9, No. 4, pp. 500-508, Aug 2001.
   pdf
Architectures with parameterizable cache and bus can support large tradeoffs between performance and power. We provide simulation data showing the large tradeoffs by such an architecture for several applications, and demonstrating that the cache and bus should be configured simultaneously to find the optimal solutions. Furthermore, we describe analytical techniques for speeding up the cache/bus power and performance evaluation by several orders of magnitude over simulation, while maintaining sufficient accuracy with respect to simulation-based approaches.

F. Vahid and A. Gordon-Ross.
A Self-Optimizing Embedded Microprocessor using a Loop Table for Low Power. International Symposium on Low Power Electronics and Design, Aug 2001, pp. 219-224.    pdf    html    slides
Describes the architecture and methodology of an embedded microprocessor that can automatically tune itself to the particular application that will run. The particular tunable component described is a loop table, similar to a loop cache except that its contents never change after the most frequent loops are detected.

F. Vahid and T. Givargis.
Platform Tuning for Embedded Systems Design. IEEE Computer, Vol. 34, No. 3, pp. 112-114, March 2001.    pdf
Provides an overview of the philosophy of our UCR Dalton Project, in particular, the idea of tuning a programmable system-on-a-chip architecture to the one application that it will eventually run forever.

T. Givargis, F. Vahid and J. Henkel.
Trace-driven System-level Power Evaluation of System-on-a-chip Peripheral Cores. Asia South-Pacific Design Automation Conference (ASP-DAC), pp. 306-311, January 2001.    pdf    html
Our earlier work for fast evaluation of power consumption of general cores in a system-on-a-chip described techniques that involved isolating high-level instructions of a core, measuring gate-level power consumption per instruction, and then annotating a system-level simulation model with the obtained data. In this work, we describe a method for speeding up the evaluation further, through the use of instruction traces and trace simulators for every core, not just microprocessor cores. Our method shows noticeable speedups at an acceptable loss of accuracy. We show that reducing trace sizes can speed up the method even further. The speedups allow for more extensive system-level power exploration and hence better optimization.

G. Stitt, F. Vahid, T. Givargis, R. Lysecky.
A First-step Towards an Architecture Tuning Methodology for Low Power. Compilers, Architectures, and Synthesis for Embedded Systems (CASES'00), pp. 187-192, November 2000.    pdf    html    slides
We describe an automated environment to assist a system-on-a-chip designer to tune a microprocessor core to a particular application program that will run on the microprocessor, and vice-versa, with the goal of reducing embedded system power consumption. We limit such tuning to modifications that do not change the microprocessor instruction set, thus avoiding the large costs that would come with such a change. Our tuning environment for the 8051 microcontroller is freely-available on the web.

T. Givargis, F. Vahid and J. Henkel.
Instruction-based System-level Power Evaluation of System-on-a-chip Peripheral Cores. IEEE/ACM International Symposium on System Synthesis (ISSS), pp. 163-169, September 2000.    pdf    html    slides
We propose a new technique, suitable for a variety of cores like peripheral cores, that is the first to combine gate-level power data with a system-level simulation model written in C++ or Java. For that purpose, we investigated peripheral cores and decomposed their functionality into so-called instructions. Our technique addresses a core-based system design paradigm. We show that our technique is sufficiently accurate for making power-related system-level design decisions, and that its computation time is orders of magnitude smaller than lower-level simulation approaches.

R. Lysecky, F. Vahid, T. Givargis.
Experiments with the Peripheral Virtual Component Interface. International Symposium on System Synthesis (ISSS), pp. 221-224, September 2000.    pdf    html    slides
The Peripheral Virtual Component Interface, or PVCI, is a standard intended to simplify the interfacing of peripheral cores to on-chip buses in a system-on-a-chip, by standardizing the interface between a core's internals and its bus wrapper. We provide results of experiments intended to determine the power, performance, and size overhead associated with using a PVCI bus wrapper versus using a non-PVCI bus wrapper, and versus using no bus wrapper at all. The results demonstrate that using a bus wrapper may result in only small performance, power and size overhead versus using no wrapper, though even that performance overhead can be reduced or eliminated using pre-fetching. The results also demonstrate that using a PVCI bus wrapper yields no significant additional power, performance or size overhead compared with a non-PVCI bus wrapper.

T. Givargis and F. Vahid.
Parameterized System Design IEEE/ACM International Workshop on Hardware/Software Codesign (CODES), pp. 98-102, May 2000.    pdf    html
Continued growth in chip capacity has led to new methodologies stressing reuse, not only of pre-designed processing components, but even of entire pre-designed architectures. To be used across a variety of applications, such architectures must be heavily parameterized, so they can adapt to those applications' differing constraints by trading off power, performance and size. We describe several parameterized system design issues, and provide results showing how a single architecture with easily configurable parameters can support a wide range of tradeoffs.

T. Givargis, F. Vahid and J. Henkel.
Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design. Design Automation and Test in Europe (DATE) Conference pp. 334-338, March 2000.    pdf    html    slides
We present a technique for fast estimation of the power consumed by the cache and bus sub-system of a parameterized system-on-a-chip design for a given application. The technique uses a two-step approach of first collecting intermediate data about an application using simulation, and then using equations to rapidly predict the performance and power consumption for each of thousands of possible configurations of system parameters, such as cache size and associativity and bus size and encoding. The estimations display good absolute as well as relative accuracy for various examples, and are obtained in dramatically less time than other techniques, making possible the future use of powerful search heuristics.

R. Lysecky, F. Vahid, T. Givargis.
Techniques for Reducing Read Latency of Core Bus Wrappers. Design Automation and Test in Europe (DATE) Conference pp. 84-91, March 2000. Best Paper Award.    pdf    html    slides
Today's system-on-a-chip designs consist of many cores. To enable cores to be easily integrated into different systems, many propose creating cores with their internal logic separated from their bus wrapper. This separation may introduce extra read latency. Pre-fetching register data into register copies in the bus wrapper can reduce or eliminate this extra latency. In this paper, we introduce a technique for automatically designing a pre-fetch unit that satisfies user-imposed register-access constraints. The technique benefits from mapping the pre-fetching problem to the well-known real-time process scheduling problem. We then extend the technique to allow user-specified register interdependencies, using a Petri Net model, resulting in even more efficient pre-fetch schedules.

T. Givargis, F. Vahid and J. Henkel.
A Hybrid Approach for Core-Based System-Level Power Modeling. Asia South-Pacific Design Automation Conference (ASP-DAC), pp. 141-145, January 2000.    pdf    html
Describes a technique for obtaining fast yet accurate power estimations of core-based systems. The main idea is to use an object-oriented language (C++ or Java) to create a system-level model , modeling each core as an object, and extending each object with power-estimation methods based on statistics from low-level power data of a synthesized version of the core. By executing the system-level model, which runs about 1000x faster than gate-level simulation, we obtain very accurate power estimates.

T. Givargis, J. Henkel and F. Vahid.
Interface and Cache Power Exploration for Core-Based Embedded System. International Conference on Computer-Aided Design (ICCAD), pp. 270-273, November 1999.    pdf    html
Demonstrates, through experiments on four applications, the large power, performance and size tradeoffs possible just by varying architectural parameters relating to cache and bus for a given reference architecture. Illustrates that these parameters must be tuned to one another for each application, and thus argues for the need for a parameter exploration environment in a configure-and-execute design paradigm.

R. Lysecky, F. Vahid, T. Givargis, and R. Patel.
Pre-fetching for Improved Core Interfacing. International Symposium on System Synthesis (ISSS), pp. 51-55, November 1999.    pdf    html
Introduces a method to reduce or eliminate the extra latency that may arise when reading from a core designed with a bus wrappers for ease of retargeting to different system buses. The method involves pre-fetching registers from the core's internals to registers added in the bus wrapper, akin to caching.

F. Vahid and T. Givargis.
The Case for a Configure-and-Execute Paradigm. International Workshop on Hardware/Software Codesign (CODES), pp. 59-63, May 1999.    pdf    html
Provides an argument, supported by data obtained by various researchers, in favor of building systems-on-a-chip by configuring a pre-designed reference design already in silicon, rather than building systems by connecting large numbers of cores.

E. Hwang and F. Vahid and Y.C. Hsu.
FSMD Functional Partitioning for Low Power
Design Automation and Test in Europe (DATE) Conference pp. 22-28, March 1999.

F. Vahid.
Techniques for Minimizing and Balancing I/O during Functional Partitioning
IEEE Transactions on CAD, Vol. 18, No. 1, pp. 69-75 January 1999.

F. Vahid.
Procedure Cloning: A Transformation for Improved System-Level Functional Partitioning
ACM Transactions on Design Automation of Electronic Systems, Volume 4, Number 1, pp. 70-96, 1999.

F. Vahid.
A Three-Step Approach to the Functional Partitioning of Large Behavioral Processes
International Symposium on System Synthesis, pp. 152--157, December 1998.

F. Vahid and T. Givargis.
Incorporating Cores into System-Level Specification. International Symposium on System Synthesis (ISSS), pp. 43--48, December 1998.    pdf    html
Describes a method for describing a system built from pre-designed system components (cores) at the system level, using an object-oriented language, resulting in dramatically faster simulations than approaches based on HDL's.

T. Givargis and F. Vahid.
Interface Exploration for Reduced Power in Core-Based Systems. International Symposium on System Synthesis (ISSS), pp. 117--122, December 1998.    pdf    html
Provides equations developed to enable one to explore various bus configurations in a parameterized architecture very rapidly. One simulates an application once, from which bus traffic data is accumalated, and then fed into a tool that analyzes each bus configuration in constant-time using the equations. The power or performance optimal bus can thus be quickly selected for a given application.

D. Gajski, F. Vahid, S. Narayan and J. Gong.
System-Level Exploration with SpecSyn
Design Automation Conference, pp. 812-817, June 1998.

F. Vahid, T.D.M. Le and Y.C. Hsu.
Functional Partitioning Improvements over Structural Partitioning for Packaging Constraints and Synthesis-tool Performance
ACM Transactions on Design Automation of Electronic Systems, Volume 3, Number 2, pp. 181-208, 1998.

D.D. Gajski and F. Vahid and S. Narayan and J. Gong.
SpecSyn: An Environment Supporting the Specify-Explore-Refine Paradigm for Hardware/Software System Design
IEEE Transactions on VLSI Systems, Vol. 6, No. 1, pp. 84-100, 1998.
Awarded the IEEE VLSI Transactions Best Paper Award, June 2000.


F. Vahid and S. Narayan.
Guest Editors' Introduction to the Special Issue on ISSS'96
ACM Transactions on the Design Automation of Electronic Systems, Vol. 2, No. 4, Oct. 1997, pp. 307-311.

F. Vahid.
Port Calling: A Transformation for Reducing I/O during Multi-Package Functional Partitioning
International Symposium on System Synthesis, pp. 107--112, September 1997.

L. Tauro and F. Vahid.
Message-Based Hardware/Software Communication in HDL/C Environments
Asia-Pacific Conference on Hardware Description Languages ASP-CHDL), August 1997.

F. Vahid and L. Tauro.
An Object-Oriented Communication Library for Hardware-Software Co-Design
International Workshop on Hardware/Software Codesign (CODES), pp. 81--86, March 1997.

F. Vahid and T.D.M. Le.
Extending the Kernighan/Lin Heuristic for Hardware and Software Functional Partitioning
Kluwer Journal on Design Automation of Embedded Systems, Vol. 2, No. 2, pp. 237-261, March 1997.

F. Vahid.
Procedure Cloning: A Transformation for Improved System-Level Functional Partitioning
European Design and Test Conference, pp. 487--492, March 1997.

F. Vahid.
Modifying Min-Cut for Hardware and Software Functional Partitioning
International Workshop on Hardware/Software Codesign, pp. 43--48, March 1997.

F. Vahid.
I/O and Performance Tradeoffs with the FunctionBus during Multi-FPGA Partitioning
International Symposium on Field-Programmable Gate Arrays, pp. 27-34, February 1997.

F. Vahid and T.D.M. Le and Y.C. Hsu.
A Comparison of Functional and Structural Partitioning
International Symposium on System Synthesis, pp. 121-126, November 1996.

F. Vahid and T.D.M. Le.
Towards a Model for Hardware and Software Functional Partitioning
International Workshop on Hardware/Software Codesign, pp. 116-123, March 1996.

D. Gajski and S. Narayan and L. Ramachandran and F. Vahid and P. Fung.
System Design Methodologies: Aiming at the 100 h Design Cycle
IEEE Transactions on VLSI Systems, Vol. 4, No. 1, pp. 70-82, 1996.

F. Vahid and D.D. Gajski.
Closeness Metrics for System-Level Functional Partitioning
European Design Automation Conference, pp. 328-333, September 1995.

F. Vahid and D.D. Gajski.
Clustering for Improved System-Level Functional Partitioning
International Symposium on System Synthesis, pp. 28-33, September 1995.

F. Vahid.
Procedure Exlining: A Transformation for Improved System and Behavioral Synthesis
International Symposium on System Synthesis, pp. 84-89, September 1995.

F. Vahid.
Procedure Exlining: A New System-Level Specification Transformation
European Design Automation Conference -- EuroVHDL, pp. 508-513, September 1995.

F. Vahid and D. Gajski.
Incremental Hardware Estimation during Hardware/Software Functional Partitioning
IEEE Transactions on VLSI Systems, Vol. 3, No. 3, pp. 459-464, September 1995.

F. Vahid and S. Narayan and D. Gajski.
SpecCharts: A VHDL Front-End for Embedded Systems
IEEE Transactions on CAD, Vol. 14, No. 6, pp. 694-706, 1995.

F. Vahid and D.D. Gajski.
SLIF: A Specification-Level Intermediate Format For System Design
European Design and Test Conference, pp. 185-189, March 1995.


D. Gajski and F. Vahid.
Specification and Design of Embedded Software-Hardware Systems
IEEE Design & Test of Computers, Vol. 12, No. 1, Spring 1995, pp. 53-67.

F. Vahid and J. Gong and D.D. Gajski.
A Binary-Constraint Search Algorithm for Minimizing Hardware during Hardware-Software Partitioning
European Design Automation Conference -- EuroDAC, pp. 214-219, September 1994.

F. Vahid, S. Narayan and D.D. Gajski.
A Transformation Integrating VHDL Behavioral Specification with Synthesis and Software Generation
European Design Automation Conference -- EuroDAC, pp. 552-557, September 1994.

D.D. Gajski and F. Vahid and S. Narayan.
A System-Design Methodology: Executable-Specification Refinement
European Conference on Design Automation, pp. 458-463, March 1994.

D.D. Gajski and F. Vahid and S. Narayan and J. Gong
BOOK: Specification and Design of Embedded Systems
Title page, Contents, and Preface
Online slides
Prentice Hall, 1994.
Perhaps the first textbook on embedded system design.

F. Vahid, and D. Gajski.
Specification Partitioning for System Design
Design Automation Conference, pp. 219-224, June 1992.

Pubs from before 1994 not listed.

F. Vahid and S. Lysecky. Embedded electronics building blocks for user-configurable monitor/control networks. U.S. patent 7555658, May 10, 2005.

F. Vahid, R. Lysecky, G. Stitt. Warp Processor for Dynamic Hardware/Software Partitioning. US Patent 7,356,672, May 28, 2004.

J. Henkel, T. Givargis, F. Vahid, Method for core-based system-level power modeling using object-oriented techniques. U.S. Patent #6,865,526, June 24, 2000.

Talks (not associated with conference papers above)

Getting Students to Earnestly Do Reading, Studying, and Homework in an Introductory Programming Class , SIGCSE Technical Symposium, Seattle, March 2017.
Effectiveness of Interactive Web-Native Content vs. Online Textbooksasee_static_vs_interactive_061514_925pm_FV.pptx, ASEE Annual Conference, Indianapolis, June 2014 (Best paper award).
Zyante's zyBooks , SJSU's NSF Workshop on MOOCs and Online Technologies, June 2014 (also UCR Innovation Day, May 2014).
Building Fake Body Parts: Digital Mockups , Texas A&M, Feb 2013 (also U Arkansas, Oct 2013).
Embedding-Based Placement of Processing element Networks on FPGAs for Physical Model Simulation , ACM Symp on FPGAs, 2013. Digital mockups video (ventillator).
Building Fake Body Parts: Digital Mockups -- UCR CSE Advisory Board Meeting, April 2012
Power to the people: Tools for user-configurable in-home assistive monitoring -- UCR CSE Advisory Board Meeting, April 2012
Engaging students via virtual lab and shorter textbooks, and the evolution towards online courses -- UC Online Course meeting, Berkeley, June 2011.   Virtual lab video
Portability for FPGA Applications: Warp Processing and SystemC Bytecode -- Univ. of Texas, Austin, ECE, July 2009
JIT FPGA Ideas -- Xilinx, San Jose, CA, June 2009
Portable FPGA Applications: Warp Processing and SystemC Bytecode -- Keynote talk, Reconfigurable Architectures Workshop (RAW), 2009, Rome, Italy
Warp Processing -- Univ. of California, San Diego, Dept. of CS&E, Nov 2008
Warp Processing -- Univ. of Illinois, Urbana/Champaign, Oct 2008 (also Univ. of Washington, Sep 2008, and Microsoft Research, Redmond WA, Sep 2008)
eBlocks -- Electronic Building Blocks for Sensor-Based Systems -- SRC/NSF Virtual Immersion Architecture Workshop, Santa Cruz, July 2008
You Can Do It -- eBlocks Enabling Regular People to Build Useful Customized Sensor-Based Systems -- Riverside Community College seminar, May 2008
Warp Processing -- SRC annual review, Dallas, 2008
Self-Improving Computer Chips -- Warp Processing -- UCR CS&E Colloquium, Oct. 2007
Standard Binaries for FPGAs, & eBlocks -- NSF's Cyber-Physical Workshop, July 2007
SensorBlocks -- UCR's College of Engineering TechHorizons, 2007
Warp Processing -- SRC annual review, Carnegie Mellon Univ., 2007
Soft Core Customization and other UCR FPGA Research Xilinx, July 2006
The New Software: FPGAs University of Arizona, ECE, April 2006
Warp Processors -- Freescale, April 2006
Warp Processing: Dynamic Transparent Conversion of Binaries to Circuits -- Notre Dame, CS, Mar 2006
Warp Processing -- SRC annual review, Ohio State Univ., 2006
Warp Processor: A Dymamically Reconfigurable Coprocessor -- Talk at Intel's System Design Symposium (San Jose), Nov. 2005
Supercomputing in a Pencil Tip -- Talk at UCR's Engineering Industry Day, Oct 2005
Silicon prototyping issues -- Panel talk at Intel, May 2005
eBlocks -- Talk at UCSD, April 2005
eBlocks -- Talk at Intel, September 2004
Warp Processors -- Distinguished Lecture at ASU, April 2004
Warp Processors -- Talk at IBM Research, Yorktown Heights, Apr 2004
Warp Processors -- SRC annual review talk, March 2004
Self-Improving Configurable IC Platforms -- SRC annual review talk, February 2003
Improving Embedded System Software Speed and Energy using Microprocessor/FPGA Platform ICs -- UCR colloquium talk, October 2002
New Opportunities with Platform-Based Design -- Keynote talk at ESCODES'02
System-on-a-Chip Platform Tuning for Embedded Systems -- given at 2002 Southern California Embedded Systems Seminar
Recent Results at UCR with Configurable Cache and Hw/Sw Partitioning -- given at Triscend Corp., September 2002.

For publications supported by NSF awards: Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation. Back to Frank Vahid's home page


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