Sunday, February 9 |
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Conference reception (7:30 pm) Made possible by Cal-(IT)2 and the HSSoE at UCI.
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Monday, February 10 |
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Welcome (8:45am - 9:00am)
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Keynote I (9:00am - 10:00am) Chair: Laxmi Bhuyan
Billion Transistor Chips in Mainstream Enterprise Platforms
of the Future. |
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Break (10:00am - 10:30am) | |
Session 1: Multithreading (10:30am - 12:00n) Chair: Antonio Gonzalez Variability in Architectural
Simulations of Multi-threaded Workloads Mini-threads: Increasing
TLP on Small-Scale SMT Processors Front-End Policies
for Improved Issue Efficiency in SMT Processors |
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Lunch (12:00n - 1:30pm) | |
Session 2: Branch Prediction (1:30am - 3:00pm) Chair: Susan Eggers Reconsidering Complex
Branch Predictors Incorporating Predicate
Information Into Branch Predictors Dynamic Data Dependence
Tracking and its Application to Branch Prediction |
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Break (3:00pm - 3:30pm) | |
Session 3: Power Efficient Designs (3:30pm - 5:30pm) Chair: Saman Amarasinghe Control Techniques
to Eliminate Voltage Emergencies in High-Performance Processors
Dynamic Voltage Scaling
with Links for Power Optimization of Interconnection Networks
Power-Aware Control
Speculation through Selective Throttling Deterministic Clock
Gating For Microprocessor Power Reduction |
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TCCA Meeting (5:30pm) |
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Tuesday, February 11 |
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Keynote II (8:30am - 9:30am) Chair: Brad Calder
Beyond Performance: Some (other) Challenges for Future Microprocessors.
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Break (9:30am - 10:00am) | |
Session 4: Superscalars (10:00am - 12:00n) Chair: David Wood
Runahead Execution: An Alternative to Very Large Instruction
Windows for Out-of-order Processors
Microarchitecture and Performance Analysis of a SPARC-V9 Microprocessor
for Enterprise Server Systems
Dynamic Optimization Of Micro-Operations |
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Luncheon (12:00n - 1:30pm)
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Session 5: Multiprocessor Systems (1:30pm - 3:00pm) Chair: Chita Das
Slipstream Execution Mode for CMP-Based Multiprocessors
Tradeoffs in Buffering Memory State for Thread-Level Speculation
in Multiprocessors
Dynamic Data Replication: An approach to Providing Fault-Tolerant
Shared Memory Clusters |
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Break (3:00pm - 3:30pm) | |
Session 6: Memory and Communication Performance (3:30pm - 5:30pm) Chair: Li-Shiuan Peh
Memory System Behavior of Java-Based Middleware
Evaluating the Impact of Communication Architecture on the
Performability of Cluster-Based Services
Hierarchical Back-Off Lock for Non-Uniform Communication Architectures
Performance Enhancement Techniques for InfiniBand Architecture
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Wednesday, February 12 |
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Keynote III (8:00am - 9:00am) Chair: Josep Torrellas
The State of State |
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Session 7: Profiling and Simulation Support (9:00am - 10:00am) Chair: Bill Mangione-Smith
Catching Accurate Profiles in Hardware
A Statistically Rigorous Approach for Improving Simulation
Methodology |
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Break (10:00am - 10:30am) | |
Session 8 (10:30am - 12:30 pm) |
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8 A: Caching
and Prefetching Chair: Soner Onder
Caches and Merkle Trees for Efficient Memory Authentication
Just Say No: Benefits of Early Cache Miss Determination
TCP: Tag Correlating Prefetchers
Cost-sensitive Cache Replacement Algorithms
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8 B: Networks
and Communication Chair: Qing Yang
Scalar Operand Networks
A Methodology for Designing Efficient On-Chip Interconnects
on Well-Behaved Communication Patterns
Inter-cluster Communication Models for Clustered VLIW
processors |