HOME - CLASSES - RESEARCH - PUBLICATIONS

Professor, Computer Science & Engineering

Vasileios Zois, Vassilis J. Tsotras and Walid A. Najjar.  Efficient Main-Memory Top-K Selection For Multicore Architectures. In Proceedings of the VLDB Endowment, October 2019

Vasileios Zois, Vassilis J. Tsotras and Wallid A. Najjar. GPU Accelerated Top-K Selection With Efficient Early Stopping, in 10th Int. Workshop on Accelerating Analytics and Data Management Systems Using Modern Processor and Storage Architectures (ADMS'19), held in conjunction with VLDB 2019, Los Angeles, CA, 26 August 2019.

Jose Rodriguez Borbon, Xiaoyin Ma, Amit K. Roy-Chowdhury, and Walid A. Najjar. Heterogeneous Acceleration of HAR Applications, in IEEE Trans. on Circuits and Systems for Video Technology, 2019. DOI PDF

Prerna Budhkar, Ildar Absalyamov, Vasileios Zois, Skyler Windh, Walid A. Najjar and Vassilis J. Tsotras. Accelerating In-Memory Database Selections Using Latency Masking Hardware Threads, in ACM Trans. on Architectures and Compiler Optimizations (TACO), Vol. 16, No. 2, April 2019. DOI PDF

Shafiur Rahman, Nael Abu-Ghazaleh and Walid Najjar. PDES-A: Accelerators for Parallel Discrete Event Simulation Implemented on FPGAs, ACM Trans. on Modeling and Computer Simulation. Vol. 29, No. 2, April 2019. DOI PDF

Vasileios Zois, Divya Gupta, Vassilis J. Tsotras, Walid A. Najjar and Jean-Francois Roy. Massively Parallel Skyline Computation For Processing-In-Memory Architectures, PACT 2018. DOI PDF

Shafiur Rahman, Nael Abu-Ghazaleh, Walid Najjar. PDES-A: a Parallel Discrete Event Simulation Accelerator for FPGAs. SIGSIM-PADS ’17, May 24–26, 2017, Singapore. PDF

Xiaoyin Ma, Jose Rodriguez Borbon, Walid A. Najjar, Amit K. Roy-Chowdhury. Optimizing Hardware Design for Human Action Recognition. 26th Int. Conf. on Field Programmable Logic and Applications, (FPL 2016), Lausanne, Switzerland, August 29 - September 2, 2016. PDF

Ildar Absalyamov, Robert J. Halstead, Prerna Budhkar, Walid A. Najjar, Skyler Windh, Vassilis J. Tsotras. FPGA-Accelerated Group-by Aggregation Using Synchronizing Caches. 12th International Workshop on Data Management on New Hardware (DaMoN 2016), Co-located with ACM SIGMOD/PODS 2016 San Francisco, USA, June 27, 2016. PDF

2015

Skyler Windh, Prerna Budhkar and Walid A. Najjar. CAMs as Synchronizing Caches for Multithreaded Irregular Applications on FPGAs. ICCAD 2015: 331-336 PDF

Skyler Windh, Xiaoyin Ma, Robert J. Halstead, Prerna Budhkar, Omar Hussaini, Zabdiel Luna, and Walid A. Najjar. High Level Language Tools for Reconfigurable Computing in Proceedings of the IEEE No. 3, Vol. 103. [DOI PDF]

Edward B. Fernandez, Jason Villarreal, Stefano Lonardi, and Walid A. Najjar. FHAST: FPGA-based acceleration of Bowtie in hardware, in IEEE/ACM Transactions on Computational Biology and Bioinformatics, Issue 99, Feb. 2015. [PDF DOI]

Robert J. Halstead, Ildar Absalyamov, Walid A. Najjar and Vassilis J. Tsotras. FPGA-based Multithreading for In-Memory Hash Joins, in 7th Biennial Conference on Innovative Data Systems Research (CIDR 15), January 4-7, 2015, Asilomar, California. [PDF SLIDES]

2014

Robert J. Halstead, Walid A. Najjar and Omar Huseini. SpVM Acceleration with Latency Masking Threads on FPGAs. Technical Report UCR-CSE-2014-04001 [PDF]

Xiaoyin Ma, Walid A. Najjar, Amit K. Roy-Chowdhury. Evaluation and Acceleration of High-Throughput Fixed-Point Object Detection on FPGAs. In IEEE Transactions on Circuits and Systems for Video Technology, 2014. [PDF DOI]

Roger Moussalli, Ildar Absalyamov, Marcos R. Vieira, Walid A. Najjar, Vassilis J. Tsotras. High Performance FPGA and GPU Complex Pattern Matching Over Spatio-Temporal Streams, in GeoInformatica, August 2014. [PDF DOI]

Robert J. Halstead, Jason Villarreal and Walid A. Najjar. Compiling Irregular Applications for Reconfigurable Systems, in Int. J. of High-Performance Computing and Networking Vol 7 No 4, May 2014. [PDF LINK]

Xiaoyin Ma, Walid Najjar and Amit Roy-Chowdhury. High-Throughput Fixed-Point Object Detection on FPGAs in 22nd IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM). May 11-13, Boston, Massachusetts.[ PDF DOI]

Roger Moussalli, Mariam Salloum, Robert J. Halstead, Walid A. Najjar and Vassilis J. Tsotras. A Study on Parallelizing XML Path Filtering Using Accelerators, in ACM Transaction on Embedded Computer Systems, Volume 13 Issue 4, February 2014. [DOI]

2013

Xi Luo, Walid A. Najjar, and Vagelis Hristidis. Efficient Near-Duplicate Document Detection using FPGAs, in The First Workshop on Benchmarks, Performance Optimization, and Emerging hardware of Big Data Systems and Applications (BPOE 2013). In conjunction with 2013 IEEE Int. Conference on Big Data, October 8, 2013, Silicon Valley, CA, USA.[PDF]

Robert Halstead and Walid A. Najjar. Compiled Multithreaded Data Paths on FPGAs for Dynamic Workloads, in Proc. Int. Conf. on Compilers Architectures and Synthesis for Embedded Systems (CASES), Sept. 29 - Oct. 4, 2013, Montreal, Canada. [PDF]

Ildar Absalyamov, Roger Moussalli, Vassilis Tsotras and Walid A. Najjar. High-Performance Holistic XML Twig Filtering Using GPUs, in Proc. 4th. Int. Workshop on Accelerating Data Management Systems (ADMS), Riva del Garda, Italy, August 26, 2013. [PDF]

Roger Moussalli, Marcos Vieira, Walid A. Najjar and Vassilis Tsotras. Stream-Mode FPGA Acceleration of Complex Pattern Trajectory Querying, in Proceedings 13th Int. Symposium on Spatial and Temporal Databases (SSTD), Munich, Germany, August 21-23, 2013. (BEST PAPER AWARD). [PDF]

Walid A. Najjar and Jason Villarreal. FPGA Code Accelerators - The Compiler Perspective, in ACM/IEEE Design Automation Conference, June 2013, Austin TX. [PDF]

Roger Moussalli, Walid A. Najjar, Xi Luo and Amna Khan. A High Throughput No-Stall Hardware Golomb-Rice Decoder, in Proceedings 21st Annual Int. IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Seattle, Washington, April 28-30 2013. [PDF]

2012

Edward B. Fernandez, Walid A. Najjar, Stefano Lonardi, Jason Villarreal. Multithreaded FPGA Acceleration of DNA Sequence Mapping, in Proc. of IEEE 2012 High Performance Extreme Computing Conference, Waltham, MA, September 11-12, 2012. [PDF]   

2011

Robert Halstead, Jason Villarreal and Walid A. Najjar. Exploring Irregular Memory Accesses on FPGAs, IAAA - Workshop on Irregular Applications: Architectures & Algorithms, held in conjunction with Supercomputing 2011 (SC'11) November, 2011, Seattle, WA. [DOI] [PDF]

Roger Moussalli, R.obert Halstead, Mariam Salloum, Walid A. Najjar and Vassilis J. Tsotras. Efficient XML Path Filtering Using GPUs, in Proc. Sec. Int. Workshop on Accelerating Data Management Systems (ADMS 2011), Seattle, WA, Sept. 2011. [PDF]

Edward B. Fernandez, Walid A. Najjar and Stefano Lonardi. String Matching in Hardware Using the FM Index, in Proc. 19th Ann. IEEE Int. Symp. on Field-Programmable Custom Computing Machines (FCCM 2011), Salt Lake City, UT, May 2011. (DOI: dx.doi.org/10.1109/FCCM.2011.55). [PDF]

Roger Moussalli, Mariam Salloum, Walid A. Najjar and Vassilis J. Tsotras. Massively Parallel XML Twig Filtering Using Dynamic Programming on FPGAs in Proc. Int. Conf. on Data Engineering 2011 (ICDE), Hanover, Germany. [PDF]

2010

Robert Halstead, Jason Villarreal, Roger Moussalli and Walid A. Najjar. Is There A Tradeoff Between Programmability and Performance? In 2010 Asilomar Conference on Signals, Systems, & Computers, Asilomar, CA, November 2010. (DOI: dx.doi.org/10.1109/ACSSC.2010.5757683). [PDF]

Jason Villarreal, Adrian Park, Roby Atadero, Walid A. Najjar and Glen Edwards. Programming the Convey HC-1 with ROCCC 2.0 in The First Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL 2010), Atlanta, Georgia, December 5, 2010. Co-located with MICRO-43. [PDF]

Doruk Sart, Abdullah Mueen, Walid A. Najjar, V. Niennattrakul, and Eamonn Keogh. Accelerating Dynamic Time Warping Subsequence Search with GPUs and FPGAs, in Int. Conf. on Data Mining, Sydney, Australia, Dec. 2010. (DOI: dx.doi.org/10.1109/ICDM.2010.21). [PDF]

A. Betul Buyukkurt, Jason Villarreal, Walid A. Najjar. Impact of High Level Transformations within the ROCCC Framework. In ACM Trans. on Architecture and Code Optimization, 7, 4, Article 7 (December 2010). [PDF]

Edward Fernandez, Walid A. Najjar and Stefano Lonardi. Exploration of Short Reads Mapping in Hardware in Proc. 20th Int. Conf. on Field Programmable Logic and Applications (FPL), Milano, ITALY, Aug. 2010. (DOI: dx.doi.org/10.1109/FPL.2010.78) [PDF]

Jason Villarreal, Adrian Park, Walid A. Najjar and Robert Halstead. Designing Modular Hardware Accelerators in C With ROCCC 2.0, in The 18th An. Int. IEEE Symp. on Field-Programmable Custom Computing Machines (FCCM), Charlotte, NC, May 2010. [PDF]

Roger Moussalli, Mariam Salloum, Walid A. Najjar and Vassilis Tsotras. Accelerating XML Query Matching Through Custom Stack Generation on FPGAs, Proc. Int. Conf. on High-Performance Embedded Architectures and Compilers, January 25-27, 2010, Pisa, Italy. [PDF]

Walid A. Najjar and Jason Villarreal. Modular Design of FPGA-Based Accelerators in C, Military and Aerospace Programmable Logic Devices (MAPLD), NASA Goddard Space Flight Center, Greenbelt, MD, August 2009.

Walid A. Najjar and Jason Villarreal. Reconfigurable Computing in the New Age of Parallelism. SAMOS Workshop, July 2009. [PDF]

Dinesh C. Suresh, Banit Agrawal, Walid A. Najjar and Jun Yang. Tunable and Energy Efficient Bus-Encoding Techniques, in IEEE Trans. on Computers, Vol. 58, No. 8, August 2009. (DOI: dx.doi.org/10.1109/TC.2009.39). [PDF]

Abishek Mitra, Marcos Vieira, Petko Balakov, Vassilis Tsotras and Walid A. Najjar. Boosting XML Filtering Through A Scalable FPGA-based Architecture, in Fourth Biennial Conference on Innovative Data Research, Asilomar, CA, January 2009. [PDF]

Dinesh C. Suresh, Banit Agrawal, Jun Yang and Walid A. Najjar. Energy efficient encoding techniques for off-chip data buses. ACM Trans. Embedd. Comput. Syst. 8, 2, Article 9 (January 2009), 23 pages. http://doi.acm.org/10.1145/1457255.1457256 [PDF]

J. Villarreal and W. A. Najjar. Compiled Hardware Acceleration of Molecular Dynamics Code, in Int. Conf. on Field Programmable Logic and Applications (FPL 08), Heidelberg, Germany, September 2008.

A. B. Buyukkur and W. A. Najjar. Compiler Generated Systolic Arrays For Wavefront Algorithm Acceleration on FPGAs, in Int. Conf. on Field Programmable Logic and Applications (FPL 08), Heidelberg, Germany, September 2008.

M. Wirthlin, D. Poznanovic, P. Sundararajan, A. Coppola, D. Pellerin, W. A. Najjar, R. Bruce, M. Babst, O. Prichard, P. Palazzari and G. Kuzmanov. OpenFPGA CoreLib Core Library Interoperability Effort, in Parallel Computing, Vol. 34, No. 4, pp. 231-244, Elsevier.

Z. Guo, A. B. Buyukkurt, J. Cortes, A. Mitra, W. A. Najjar. A Compiler Intermediate Representation for Reconfigurable Fabrics in Int. Journal of Parallel Programming (IJPP), Springer (http://www.springerlink.com/content/u124q758h231414k/).

Z. Guo, W. A. Najjar, A. B. Buyukkurt. Efficient Hardware Code Generation for FPGAs, in ACM Trans. on Architecture and Compiler Optimizations (TACO) Vol. 5, No. 1, Article 6, May 2008, 26 pages, ACM. http://doi.acm.org/10.1145/1369396.1369402 -

A. Mitra, W, A. Najjar, L. Bhuyan. Compiling PCRE to FPGA for Accelerating SNORT IDS, in the ACM/IEEE Symposium on Architecture for Networking and Communication Systems (ANCS), Orlando, FL, Dec. 2007.

K. Schleupen, S. Lekuch, R. Mannion, Z. Guo, W. A. Najjar and F. Vahid. Dynamic Partial FPGA Reconfiguration in a Prototype Microprocessor System, in Int. Conf. on Field Programmable Logic (FPL) Amsterdan, The Netherlands, August 2007. [DOI] 

J. Villarreal, J. Cortes, and W. A. Najjar, Compiled Code Acceleration of NAMD on FPGAs, in Reconfigurable Systems Summer Institute, Urbana, IL, July 2007.

A. Mitra, Y. Ge and W. A. Najjar. Performance Analysis of SGI RASC RC100 Blade on 1D DWT, in Reconfigurable Systems Summer Institute, Urbana, IL, July 2007.

W. A. Najjar. Experience with the ROCCC Compiler on RASC, SGI User Group Conference, Minneapolis, MN, May 2007.

A. Gordon-Ross, P. Vianna, F. Vahid, W. A. Najjar and E. Baros. A One-Shot Configurable-Cache Tuner for Improved Energy and Performance,, in AM/IEEE DATE 2007, Nice, France.[DOI] 

G. Stitt, F. Vahid and W. A. Najjar. A Code Refinement Methodology for Performance-Improved Synthesis from C, in IEEE Int. Conf. on Computer-Aided Design (ICCAD), San Jose, CA, November 2006.

A. Mitra, Z. Guo, A. Banerjee, W. A. Najjar. Dynamic Co-Processor Architecture for Software Acceleration on CSoCs, IEEE Int. Conf. on Computer Design (ICCD), San Jose, CA, October 2006. [DOI] 

S. Lin, D. Zeinaliopur-Yazti, V. Kalogeraki, D. Gunopoulos and W. A. Najjar. Efficient Indexing Data Structures for Flash-Based Sensor Devices, in ACM Trans. on Storage Vol.2, No. 4, pp. 468-503, November 2006.

Z. Guo, A. Mitra and W. A. Najjar. Automation of IP Core Interface Generation for Reconfigurable Computing, in 16th Int. Conf. on Field Programmable Logic and Applications (FPL 2006), Madrid, Spain, August 2006. [DOI] 

Z. Guo and W. A. Najjar. A Compiler Intermediate Representation for Reconfigurable Fabrics, in 16th Int. Conf. on Field Programmable Logic and Applications (FPL 2006), Madrid, Spain, August 2006.

D. Kulkarni, W. A. Najjar, R. Rinker, F. Kurdahi. Compile-time Area Estimation for LUT-based FPGAs. In ACM Trans. on Design Automation of Electronic Systems, January 2006.

D. Suresh, Z. Guo, W. A. Najjar. Automatic compilation framework for Bloom filter based intrusion detection, Int. Workshop On Applied Reconfigurable Computing (ARC 2006) Delft, The Netherlands, March 1-3, 2006.

B. A. Buyukkurt, Z. Guo, W. A. Najjar. Impact of Loop Unrolling on Throughput, Area and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs, Int. Workshop On Applied Reconfigurable Computing (ARC 2006) Delft, The Netherlands, March 1-3, 2006. 

D. Zeinalipour-Yazti, S. Lin, V. Kalogeraki, D. Gunopulos, W. A. Najjar. MicroHash: An Efficient Index Structure for Flash-Based Sensor Devices, in 4th USENIX Conf. on Files and Storage Technologies (FAST 2005), San Francisco, CA, December 2005.

D. C. Suresh, B. Agrawal, W. A. Najjar, J. Yang. VALVE: Variable Length Value  Encoding for Off-Chip Data Buses, IEEE Int. Conf. on Computer Design (ICCD), San Jose, CA, October 2005.

S. Neema, A. Mitra, A. Banerjee, W. A. Najjar, D. Zeinalipour-Yazti, D. Gunopulos, V. Kalogeraki. NODES: A Novel System Design For Embedded Sensor Systems, SPOTS Track, IPSN 2005, Los Angeles, CA.

D. Zeinalipour-Yazti, V. Kalogeraki, D. Gunopulos, A. Mitra, A. Banerjee , W. A. Najjar. Towards In-Situ Data Storage in Sensor Databases, PCI 2005, Vollos. Greece.

A. Mitra, A. Banerjee, W. A. Najjar, D. Zeinalipour-Yazti, D.Gunopulos, V. Kalogeraki. High Performance, Low Power Sensor Platforms Featuring Gigabyte Scale Storage, In Proceedings of Third Int. Workshop on Measurement, Modeling, and Performance Analysis of Wireless Sensor Networks (SenMetrics), San Diego, CA, July 2005.

A. Banerjee, A. Mitra, W. A. Najjar, D. Zeinalipour-Yazti, V. Kalogeraki and D. Gunopulos. Co-S: A High Performance Co-processing Sensor Architecture for Offloading Sensing and Data Processing, Second Annual IEEE Communications Society Conference on Sensor and Ad Hoc Communications and Networks (SECON), Santa Clara, CA, September 2005. 

C. Zhang, F. Vahid, J. Yang and W. A. Najjar. A Way-Halting Cache for Low-Energy High-Performance Systems. ACM Trans. on Architecture and Code Optimizations (TACO). Volume 2, No. 1, March 2005, Pages 34-54.

D.C. Suresh, B. Agrawal, W. A. Najjar and J. Yang, A Tunable Bus Encoder for Off-chip Data Buses, in Int. Symposium on Low Power Electronics Design (ISLPED 2005), San Diego, CA, August 2005.

D.C. Suresh, W. A. Najjar and J. Yang, Power Efficient Instruction Caches for Embedded Systems, in Embedded Computer Systems: Architectures, MOdeling and Simulation, (SAMOS V), Samos, Greece, July 2005.

C. Zhang, F. Vahid and W. A. Najjar. A highly configurable cache for low energy embedded systems. ACM Trans. on Embedded Computing Systems. Vol. 4 No. 2. May 2005. Pages 363-38.

G. Stitt, Z. Guo, F. Vahid, and W. A. Najjar. Techniques for Synthesizing Binaries to an Advanced Register/Memory Structure. ACM/SIGDA Symp. on Field Programmable Gate Arrays (FPGA), Feb. 2005.

D. Zeinalipour-Yazti, S. Neema, D. Gunopulos, V. Kalogeraki, W. A. Najjar. Data Acquisition in Sensor Networks with Large Memories. 1st IEEE Int. Workshop on Networking Meets Databases (NetDB), in cooperation with 21st IEEE Conference on Data Engineering (ICDE 2005) Tokyo, Japan, April 8-9, 2005.

Z. Guo, B. Buyukkurt, W. A. Najjar and K. Vissers. Optimized Generation of Data-Path from C Codes. In ACM/IEEE Design Automation and Test Europe (DATE), Munich, Germany, March 2005.

C. Zhang, F. Vahid, J. Yang, and W. A. Najjar. A Way-Halting Cache for Low-Energy High Performance Systems, IEEE Int. Symp. on Low Power Electronics and Design (ISLPED), Aug 2004.

Z. Guo, A. B. Buyukkurt and W. A. Najjar. Input Data Reuse In Compiling Window Operations Onto Reconfigurable Hardware, Proc. ACM Symp. On Languages, Compilers and Tools for Embedded Systems (LCTES), Washington DC, June 2004.

Z. Guo, W. A. Najjar, F. Vahid and K. Vissers. A Quantitative Analysis of the Speedup Factors of FPGAs over Processors, In. Symp. on Field-Programmable gate Arrays (FPGA), Monterrey, CA, February 2004.

D. C. Suresh, J. Yang, C. Zhang, B. Agrawal, W. A. Najjar. FV-MSB: A Scheme for Reducing Transition Activity on Data Buses, Int. Conf. On High Performance Computing, December 2003, Hyderabad, India.

D. C. Suresh, B. Agrawal, J. Yang, W. A. Najjar, L. Bhuyan. Power Efficient Encoding Techniques for Off-chip Data Buses, Int. Conf. on Compilers, Architectures and Synthesis for Embedded Systems (CASES), October 2003, San Jose, CA.

C. Zhang, F. Vahid, J. Yang and W. A. Najjar. A Way-Halting Cache for Low-Energy High-Performance Systems. IEEE Computer Architecture Letters. Sept. 2003

S. Cotterell, F. Vahid, W. A. Najjar, H. Hsieh. First Results with eBlocks: Embedded Systems Building Blocks. ISSS/CODES 2003, Newport Beach, CA, October 2003

D. C. Suresh, W. A. Najjar J. Villareal, G. Stitt and F. Vahid. Profiling Tools for Hardware/Software Partitioning of Embedded Applications. Proc. ACM Symp. On Languages, Compilers and Tools for Embedded Systems (LCTES), San Diego, CA, June 2003.

C. Zhang, F. Vahid and W. A. Najjar. A Highly Configurable Cache Architecture for Embedded Systems. Proc. Int. Symp. On Computer Architecture (ISCA 2003), San Diego, CA, June 2003.

C. Zhang, F. Vahid, W. A. Najjar. Energy Benefits of a Configurable Line Size Cache for Embedded Systems,  Int. Symposium on VLSI, Feb.2003. (DOI http://dx.doi.org/10.1109/ISVLSI.2003.1183357)

Z. Guo, D. C. Suresh, W. A. Najjar. Programmability and Efficiency in Reconfigurable Computer Systems, Workshop on Software Support for Reconfigurable Systems, held in conjunction with the Int. Conf. on High-Performance Computer Architecture, Anaheim, CA, February 2003

C. Zhang, F. Vahid, J. Yang and W. A. Najjar. A Way-Halting Cache for Low-Energy High-Performance Systems. IEEE Computer Architecture Letters. Sept. 2003

G. Venkataramani, W. A. Najjar, F. Kurdahi, N. Bagherzadeh, W. Bohm and J. Hammes. Automatic Compilation to a Coarse-grained Reconfigurable System-on-Chip. ACM Trans. on Embedded Computing Systems, November 2003.

W. A. Najjar, W. Bohm, B. Draper, J. Hammes, R. Rinker, R. Beveridge, M. Chawathe and C. Ross. From Algorithms to Hardware, A High-Level Language Abstraction for Reconfigurable Computing. IEEE Computer, August 2003.

D. C. Suresh, S. Mohanty, W. A. Najjar, L.  Bhuyan and F. Vahid. Loop level analysis of security and network application. Sixth Workshop on Computer Architecture Evaluation using Commercial Workloads, held in conjunction with the Int. Conf. Of High-Performance Computer Architecture Anaheim, CA, February 2003

D. Kulkarni, W. A. Najjar, R. Rinker, and F. Kurdahi, Fast Area Estimation to Support Compiler Optimizations in FPGA-based Reconfigurable Systems, IEEE Symp. on Field-Programmable Custom Computing Machines (FCCM), Napa, CA, April 2002.

W. Bohm, R. Beveridge, B. Draper, C. Ross, M. Chawathe, and W. A. Najjar, Compiling ATR Probing Codes for Execution on FPGA Hardware.  IEEE Symp. on Field-Programmable Custom Computing Machines, Napa Valley, CA, April 21-24, 2002

J. Villarreal, D. Suresh, G. Stitt, F. Vahid and W. A. Najjar. Improving Software Performance with Configurable Logic, Kluwer Journal on Design Automation of Embedded Systems, November 2002, Vol. 7, No. 4, pp.325 -339.

W. Bohm, J. Hammes, B. Draper, M. Chawathe, C. Ross, R. Rinker, W. A. Najjar. Mapping a Single Assignment Programming Language to Reconfigurable Systems, The Journal of Supercomputing, Volume 21, pages 117-130, 2002.

J. Hammes, A.P.W. Bohm, C. Ross, M. Chawathe, B. Draper and W. A. Najjar, High Performance Image Processing on FPGAs.  Los Alamos Computer Science Institute Symp., Santa Fe, NM, Oct. 15-18, 2001.

B. Draper, W. Bohm, J. Hammes, W. A. Najjar, R. Beveridge, C. Ross, M. Chawathe, M. Desai, J. Bins, Compiling SA-C Programs to FPGAs: Performance Results, Int. Conf. on Vision Systems, Vancouver, July 7-8, 2001. p. 220-235.

G. Venkataramani, W. A. Najjar, F. Kurdahi, N. Bagherzadeh, W. Bohm. A Compiler Framework for Mapping Applications to a Coarse-grained Reconfigurable Computer Architecture, in Int. Conf. on Compiler, Architecture and Synthesis for Embedded Systems (CASES 2001), Atlanta, GA, November 2001.

A.P.W. Bohm, B. Draper,  W. A. Najjar, J. Hammes, R. Rinker, M. Chawathe, C. Ross. One-Step Compilation of Image Processing Algorithms to FPGAs, in IEEE Symp. on Field-Configurable Custom Machines (FCCM 2001). Rohnert Park, CA, April 30 - May 2, 2001.

J. Hammes, A.P.W. Bohm, C. Ross, M. Chawathe, B. Draper, R. Rinker, W. A. Najjar. Loop Fusion and Temporal Common Subexpression Elimination in Window-based Loops, in Reconfigurable Architectures Workshop (RAW'01) held in conjunction with the Int. Parallel and Distributed Processing Symp. (IPDPS'01). San Francisco, CA, April 27, 2001.

D. Kumar, W. A. Najjar and P. K. Srimani. Performance Evaluation of a New Hardware Supported Multicast Scheme for K-ary N-cubes, in Workshop on Communication Architectures for Clusters (CAC'01) held in conjunction with the Int. Parallel and Distributed Processing Symp. (IPDPS'01). San Francisco, CA, April 27, 2001

D. Kumar, W. A. Najjar and P. K. Srimani. A New Adaptive Hardware Tree-Based Multicast Routing in K-Ary N-Cubes, in IEEE Trans. on Computers, Vol. 50(7), July 2001.

R. Rinker, M. Carter, A. Patel, M. Chawathe, C. Ross, J. Hammes, W. A. Najjar and A.P.W. Bohm. An Automated Process for Compiling Dataflow Graphs into Hardware. IEEE Trans. on VLSI, Vol 9(1), February 2001.

L. Roh, B. Shankar, W. Bohm, and W. A. Najjar. Resource Management in Dataflow-Based Multithreaded Execution, in Journal of Parallel and Distributed Computing 61, 581608 ( 2001 ), pages 581-608.

B. Draper, W. A. Najjar, W. Bohm, J. Hammes, R. Rinker, C. Ross, M. Chawathe, J. Bins. Compiling and Optimizing Image Processing Algorithms for FPGA's, in Int. Workshop on Computer Architecture for Machine Performance. Padova, Italy, September 11-13 2000.

R. Rinker, J. Hammes, W. A. Najjar, W. Bohm, B. Draper. Compiling Image Processing Applications to Reconfigurable Hardware, in IEEE Int. Conference on Application-specific Systems, Architectures and Processors, Boston, MA, July 10-12 2000.

J. Hammes, R. Rinker, W. Bohm, W. A. Najjar, Bruce Draper, A High Level, Algorithmic Programming Language and Compiler for Reconfigurable Systems, in 2nd Workshop on the Engineering of Reconfigurable Hardware/Software Objects (ENREGLE), part of the Int. Conf. on Parallel and Distributed Processing Techniques and Applications (PDPTA'2000), Las Vegas, NV, June 26-29 2000.

J. Hammes, R. Rinker, W. Bohm, W. A. Najjar, B. Draper, and R. Beveridge Cameron: High Level Language Compilation for Reconfigurable Systems. Conference on Parallel Architectures and Compilation Techniques, Newport Beach, CA, Oct. 12-16 1999.

J. Hammes, R. Rinker, W. Bohm, W. A. Najjar. Compiling a High--level Language to Reconfigurable Systems. Compiler and Architecture Support for Embedded Systems (CASES'99), Washington DC, Oct. 1999.

J. Bins, B.A. Draper, W.A.P. Bohm and W. A. Najjar. Precision vs. Error in JPEG Compression. Parallel and Distributed Methods for Image Processing III, Denver, CO, July 22, 1999.

D. Miller and W. A. Najjar. Combining adaptive and deterministic routing: Evaluation of a hybrid router. In 3rd Workshop on Communication, Architecture, and Applications for Network-based Parallel Computing (CANPC'99), Orlando, FA, January 1999.

W. A. Najjar, E. Lee and G. Gao, Advances in the dataflow computational model, Parallel Computing, North-Holland, Vol. 25, No. 13-14, pages 1907-1929, December 1999 (invited paper).

W. A. Najjar, B. Draper, A.P.W. Bohm, R. Beveridge. The Cameron Project: High-Level Programming of Image Processing Applications on Reconfigurable Computing Machines. In PACT'98 - Workshop on Reconfigurable Computing. Paris, FRANCE, October 1998.

D. Miller and W. A. Najjar. Empirical Evaluation of Deterministic and Adaptive Routing with Constant-Area Routers. In Proc. Int. Conf. on Parallel Architectures and Compilation Techniques (PACT'97), San Francisco, November 1997.

J-L. Gaudiot, W. Bohm, W. A. Najjar, T. DeBoni, J. Feo, and P. Miller. The Sisal model of functional programming and its implementation. In 2nd Aizu Int. Conf. on Parallel Architectures/Algorithm Synthesis, Aizu, Japan, March 1997.

J-L. Gaudiot, W. Bohm, T. DeBoni, J. Feo, P. Miller and W. A. Najjar. The Sisal Project: Real World Functional Programming; in Languages, Compilation Techniques and Run Time Systems for Scalable Parallel Systems, Recent Advances and Future Perspectives, Springer Verlag,Lecture Notes in Computer Science Series,1997.

D. Miller and W. A. Najjar. Preliminary Evaluation of a Hybrid Deterministic/Adaptive Router. In Proc. Parallel Computing, Routing and Communication Workshop (PCRCW'97), Atlanta, June 1997.

M. Annavaram and W. A. Najjar. Comparison of two storage models in data-driven multithreaded architectures. In Proc. Eight IEEE Symp. on Parallel and Distributed Processing, New Orleans, LA, October 1996.

A. Lagman and W. A. Najjar. Analysis of buffer design for adaptive routing in direct networks. In Int. Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOT'96), February 1996.

L. Roh and W. A. Najjar. Design of storage hierarchy in multithreaded architectures. In IEEE/ACM Int. Symp. on Microarchitecture (MICRO-28), November 1995.

L. Roh and W. A. Najjar. Analysis of communication and overhead reduction in multithreaded execution. In Int. Conf. on Parallel Architectures and Compilation Techniques, pages 122-130, June 1995.

B. Shankar, L. Roh, W. Bohm, and W. A. Najjar. Control of loop parallelism in multithreaded code. In Int. Conf. on Parallel Architectures and Compilation Techniques, pages 131-139, June 1995.