Dr. Laxmi N. Bhuyan

Dustinguished Professor

Computer Science and Engineering

University of California, Riverside, CA 92521

Office: 351, Winston Chung Hall
Phone: (951) 827-2244
Fax: (951) 827-4643
Email: bhuyan@cs.ucr.edu

Short Biography:

Laxmi Narayan Bhuyan is Distinguished Professor and Chairman of Computer Science and Engineering Department at the University of California, Riverside (UCR). Prior to joining UCR in January 2001, he was a professor of Computer Science at Texas A&M University (1989-2000) and Program Director of the Computer System Architecture Program at the National Science Foundation (1998-2000). He has also worked as a consultant to Intel and HP Labs.

Dr. Bhuyan received his Ph.D. degree in Computer Engineering from Wayne State University in 1982. His current research interests are in the areas of network packet processing, multiprocessor architectures, network processors and I/O architectures, high-performance IP routers, parallel and distributed processing, and performance evaluation. He has published more than 150 papers in these areas in IEEE Transactions on Computers (TC), IEEE Transactions on Parallel and Distributed Systems (TPDS), Journal of Parallel and Distributed Computing (JPDC), and many refereed conference proceedings.

Dr. Bhuyan served as the Editor-in-Chief of the IEEE Transactions on Parallel and Distributed Systems (TPDS) from 2006 to 2009. He is a past Editor of the IEEE TC, JPDC, and Parallel Computing Journal. His professional activities are too numerous to describe. To mention a few, he was the founding Program Committee Chairman of the HPCA in 1995, Program Chair of the IPDPS in 1996, General Chair of ADCOM-2001, and General Chair of HPCA-9 (2003). He was elected Chair of the IEEE Computer Society Technical Committee on Computer Architecture (TCCA) between 1995-1998.

Dr. Bhuyan is a Fellow of the IEEE, a Fellow of the ACM, a Fellow of the AAAS (American Association for the Advancement of Science), and a Fellow of the WIF (World Innovation Foundation). He has also been named as an ISI Highly Cited Researcher in Computer Science. He has received other awards such as Halliburton Professorship at Texas A&M University, and Senior Fellow of the Texas Engineering Experiment Station. He was also awarded the IEEE CS Outstanding Contribution Award in 1997. He was inducted into the Distinguished Alumni Hall of Fame of the Wayne State University College of Engineering in October 2010. He recived the Distinguished Alumnus Award from National Institute of Technology, Rourkela in 2011.

My Ph.D. Family Tree

Education and Experience

Honors and Professional Activities

Education:

Ph.D. Computer Engineering, Wayne State University, 1982
M.Sc. Electrical Engineering, REC, Rourkela, Sambalpur University, 1978
B.Sc. Electrical Engineering, REC, Rourkela, Sambalpur University, 1972

Experience:

Distinguished Professor, Department of Computer Science & Engineering, University of California at Riverside, July 2010 - Present
Chairman, Department of Computer Science & Engineering, University of California at Riverside, July 2007 - Present
Professor, Computer Science & Engineering, University of California at Riverside, January 2001 - Present
Professor, Computer Science, Texas A&M University, September 1991 - December 2000
Program Director, Computer System Architecture, NSF, September 1998 - August 2000
Consultant, Hewlett Packard Laboratories, August 1998
Consultant/Visiting Professor, Intel Corporation, July-August, 1997
Associate Professor, Computer Science, Texas A&M University, August 1989-1991
Associate Professor, The Center for Advanced Computer Studies, University of Southwestern Louisiana, 1985-August 1989
Assistant Professor, Electrical and Computer Engineering, University of Southwestern Louisiana, 1983-1985
Assistant Professor, Electrical Engineering, University of Manitoba, 1982-1983

Students Supervised:

Ph.D. Graduated

Dr. Chita R. Das , 1986, Distinguished Professor, Pennsylvania State University
Dr. Qing Yang , 1988, Distinguished Engineering Professor, University of Rhode Island
Dr. Dipak Ghosal , 1988, University of California at Davis
Dr. Hong Jiang , 1991, University of Nebraska
Dr. Ashwini Nanda , 1993, IBM TJ Watson Research Center
Dr. C.H. Chen, 1993, University of Tuskegee
Dr. Jason Ding , 1994, Cisco Systems
Dr. Yeimkuan Chang, 1995, Chung-Hua Polytechnic Institute
Dr. Phanindra Mannava, 1995, Intel Corporation
Dr. Chao Feng, 1995, Cisco
Dr. Akhilesh Kumar , 1996, Intel Corporation
Dr. Ravi Iyer , 1999, Intel Corporation
Dr. Marius Pirvu , 2000, Compaq Corporation
Dr. Nan Ni , 2000, IBM Corporation
Dr. Hu-Jun Wang , 2001, IBM Corporation
Dr. Yan Luo , 2005, University of Massachusetts at Lowell
Dr. Xiao Zhang , 2005, Qualcomm
Dr. Li Zhao , 2005, Intel Corporation
Dr. Jiani Guo , 2006, Cisco
Dr. Satya Mohanty , 2007, Cisco
Dr. Jingnan Yao , 2007, Cisco
Dr. Jia Yu , 2007, VMWare
Dr. Anirban Banerji , 2009, Start-up
Dr. Danhua Guo , 2010, Microsoft

Dr. Guangdeng Liao , 2011, Intel Research
Dr. Jilong Kuang , 2011, Samsung Research

Past/Current Research Associates:

Dr. Rabi Mahapatra , 1997 From IIT, Kharagpur
Dr. Yeimkuan Chang , 2001 From Taiwan National University
Dr. Zhiyong Xu , From University of Cincinnati
Dr. In - Bum Jung , 2003 From KAIST
Dr. Bin Liu , 2006, From Tshinghua University
Dr. Heeyeol Yu , 2009, From Texas A&M University
Dr. Qin Liu, 20, From Wuhan University

Current Ph.D. Students:

Chih-hsun Chou
Frank Yang
Mehmet Belviranli
Yi Hu
Sambit Shukla
Dong Vu

M.S. Graduates: 30

Awards:

Distinguished Alumnus Award, Hall of Fame, Wayne State University, COE, 2010
Distinguished Alumnus Award, NIT, Rourkela, 2011
ISI Highly Cited Researcher in Computer Science
Fellow of the ACM
Fellow of the IEEE
Fellow of the AAAS
Fellow of the World Innovation Foundation (WIF)
Fulbright Senior Specialist Award, 2004
IBM University Partnership Award, 1998
Golden Core Member, IEEE Computer Society, 1997
Outstanding Contribution Award, IEEE Computer Society, 1996
Senior Fellow Award, Texas Engineering Experiment Station (TEES), 1996
Haliburton Professorship Award, 1991
TEES Fellow Award, 1992, 1994

Selected Professional Activities:

Editor-in-Chief, IEEE Transactions on Parallel and Distributed Systems, January 2006-2009
Associate Editor, IEEE Trandactions on Computers, 2002-2006
Editor, Journal of Parallel and Distributed Computing, 1995-2006
Editorial Board, Parallel Computing, 1992-2006
General Co-Chairman, IEEE Int. Symposium on High-Performance Computer Architecture (HPCA9), Feb 2003
Chairman, IEEE Computer Society Technical Committee on Computer Architecture (TCCA), 1995- 1998
Associate Editor, IEEE Transactions on Parallel and Distributed Systems, 1998-1999
Editor - System Architecture, IEEE Computer Magazine, 1991- 1997
Program Co-Chairman, International Symposium on Parallel and Distributed Processing (SPDP), 1996
Program Chairman, International Symposium on High-Performance Computer Architectures (HPCA), 1995
ACM Lecturer, 1991- 1995
Distinguished Visitor, IEEE Computer Society, 1987-1990

Research Interests and Areas of Expertise:

Network Computing
Multiprocessor Architecture
Network Packet Processing and I/O architectures
P2P and Computer Networks
Internet Router and Web Server Architectures
Parallel and Distributed Systems

Current Projects:

National Science Foundation, Principal Investigator, (Co-PIs: Rajiv Gupta and Walid Najjar) SHF: Medium: Hardware/Software Partitioning for Hybrid Shared Memory Multiprocessors, September 2009 through August 2012.
National Science Foundation, Principal Investigator, CSR: Small: Core Scheduling to Improve Virtualized I/O Performance on Multi-Core Systems, September 2009 through August 2012.
National Science Foundation, Principal Investigator, Virtualizaion-Aware Architectures to Accelerate Netwok I/O Processing, September 2008 through August 2012.
National Science Foundation, Principal Investigator, Application Oriented Edge Router, September 2008 through August 2012.
Intel Corporation, CPU+NIC Architectures to Accelerate I/O Processing, July 2007 through June 2010.
National Science Foundation, Principal Investigator, Software Architectures for Distributed Web Services Based on Peer-to-Peer Technologies, October 2005 through September 2009.
Cisco, Principal Investigator, Intelligent Message Scheduling on Application Oriented Networking (AON) System, 2006, Unrestricted.

Other Recent Projects:

National Science Foundation, Principal Investigator, Acquisition of an Ultra Low-Latency Multiprocessor System with On-Board Hardware Accelerator, August 2006 through July 2009.
National Science Foundation, Principal Investigator, Scheduling in High Performance Internet Routers, Sept. 2003 through August 2008.
Intel Corporation and UC Micro, Principal Investigator, Advanced Acceleration Solutions for Next Generation Data Center Servers, 2003-2007.
Intel IXA University Program and UC Micro, Principal Investigator, Network Processor Architecture Laboratory , 2003-present.
National Science Foundation, Co-Principal Investigator, Scalable Software System for Large Internet Servers, April 2003 through March 2007 (With P. Mohapatra at UC, Davis).
National Science Foundation, Principal Investigator, ITR: Collaborative Research: Processor Architectures for Web Switches, Sept. 2002 through August 2006.
Los Alamos National Laboratory, Principal Investigator, Interface Design for High-Performance Networking, November 2003 to June 2005, (with Mart Molle).
National Science Foundation, Principal Investigator, High-Performance Internet Router Architectures, Sept. 2001 through August 2004.
Intel IXA University Program and UC Micro, Principal Investigator, Design and Application of Network Processors, 2003-2004.
National Science Foundation, Principal Investigator, High Performance Switch Architectures for CC-NUMA Multiprocessors, Sept. 1998 through Aug. 2003.
National Science Foundation, Principal Investigator, ``Cache Coherence in Wormhole Networks,'' April 1996 through August 2001.
Texas Advanced Technology Program, Principal Investigator, ``Architecture Evaluation using Commercial Workloads,'' Jan. 2000 through Dec. 2001.
IBM TJ Watson Research Center, Principal Investigator, ``Research in Shared Memory Multiprocessors,'' University Partnership Award, 1998, Unrestricted.
Texas Energy Resource Program, Co-Principal Investigator, ``Parallel Processing Algorithms for Rapid CT Scan Analysis,'' June 1998 through May 1999, (with D. Mamora).
Hewlett-Packard Co., Principal Investigator, ``Research in Shared Memory Multiprocessors, HP V-Class 16 processor Machine,'' January 1998 through December 2000, (with N. Amato and L. Rauchwerger).
Texas Advanced Technology Program, Principal Investigator, ``Fault Tolerance in Multiprocessor Arrays,'' Jan 1994 through August 1996, (with F. Lombardi).
National Science Foundation, Principal Investigator, ``Cache Architecture s for Large Shared Memory Multiprocessors,'' July 1993 through June 1997.
National Science Foundation, CISE Small Scale Institutional Infrastructure Program, Co-Principal Investigator, ``Research in Parallel and Distributed Computing,'' March 1992 through Feb 1996, (with R. Volz and U. Pooch).
International Business Machines, Principal Investigator, ``Evaluation of Cluster Architectures,'' Jan 1993 through Dec 1993.
Texas Advanced Technology Program, Co-Principal Investigator, ``An Approach to Solve the Cache Thrashing Problem,'' Jan 1992 through Dec 1993, (with Mi Lu).
Texas Instruments, Principal Investigator, ``Mapping Algorithms onto Parallel Architectures,'' 1991, Unrestricted.
National Science Foundation, Principal Investigator, ``Design and Analysis of Cache Coherence Protocols for MIN Based Multiprocessors,'' August 1990 thrugh July 1993.

Number of Publications:

Journal Publications: 57
Conference Proceedings: 116
Presentations: 50

Selected Publications:

High-Performance IP Routers:

A New IP Lookup Cache for High Performance IP Routers , ACM Design Automation Conference (DAC), Anaheim, June 2010 (with ).
A Scalable Hashing using Bloom and Fingerprint Filters for a Large Routing Table , IEEE ICNP 2009, Princeton, NJ, October 2009 (with H. Yu and R. Mahapatra).
Adaptive Max-min Fair Scheduling in Buffered Crossbar Switches Without Speedup , IEEE INFOCOM 2007, Anchorage, Alaska, May 2007 (with X. Zhang and S. Mohanty).
EaseCAM: An Energy and Storage Efficient TCAM-Based Architecture for IP Lookup , IEEE Transactions on Computers, May 2005, pp. 521-533, (With V.C. Ravikumar and R.N. Mahaptra).
An Efficient Scheduling Algorithm for Combined-Input-Crosspoint-Queued (CICQ) Switches , IEEE Globecom, Dallas, TX, November 2004, (With X. Zhang).
Deficit Round Robin Scheduling for Input-queued Switches , IEEE Journal of Selected Areas in Communications, Special Issue on High Performance Optical/Electronic Switches/Routers for High Speed Internet, May 2003, pp. 584-594, (With X. Zhang).
Shared Memory Multiprocessor Architectures for Software IP Routers, , IEEE Transactions on Parallel and Distributed Systems, Dec 2003, pp. 1240-1249, (with Yan Luo and Xi Chen)
Fair Scheduling for Input Buffered Switches , Journal of Cluster Computing, Special Issue on Communication Architecture for Clusters, Kluwer Academic Publishers, Vol.6, No.2, April 2003. (with Nan Ni)
A Cluster-based Active Router Supporting Video/Audio Stream Transcoding Service, IEEE IPDPS, Nice, April 2003.
Fair Scheduling in Internet Routers , IEEE Transactions on Computers, Special Issue on Quality of Service Issues in Internet Web Services, June 2002, pp. 686-701(with N. Ni).
Fair Scheduling and Buffer Management in Internet Routers , IEEE INFOCOM, New York, June 2002(with N. Ni).

Network Packet Processing:

A QoS Aware Multicore Hash Scheduler for Network Applications , IEEE INFOCOM, Shanghai, China, April 2011 (with D. Guo).
LATA: A Latency and Throughput-Aware Packet Processing System , ACM Design Automation Conference (DAC), Anaheim, June 2010 (with J. Kuang).
Optimizing Throughput and Latency under Given Power Budget for Network Packet Processing , IEEE INFOCOM, San Diego, CA, March 2010 (with J. Kuang).
Ordered Round Robin: An Efficient Sequence Preserving Scheduler for Network Processors , IEEE Transactions on Computers, December 2008, pp. 1690-1703 (with J. Yao and J. Guo).
Quantum-Adaptive Scheduling for Multi-Core Network Processors , International Conference on Distributed Computing Systems (ICDCS), June 2008, Beijing, China (with Y. Zhang et al).
Program Mapping onto Network Processors by Recursive Bipartitioning and Refining , 44th Design Automation Conference (DAC), San Diego, June 2007, (with Jia Yu, et al).
Low Power Network Processor Design using Clock Gating , ACM Design Automation Conference (DAC), June 2005, (with Y. Luo, et al).
An Efficient Packet Scheduling Algorithm in Network Processors , IEEE Infocom, March 2005, (with J. Guo and J. Yao).
NePSim: A Network Processor Simulator with Power Evaluation Framework , IEEE Micro, Special Issue on Network Processors, September/October 2004, (with Y. Luo et al).
TCP/IP Cache Characterization in Commercial Server Workloads , CAECW 2004, Along with HPCA-10, February 2004, (with L. Zhao et al).
Architectural Analysis and Instruction Set Optimization for Network Protocol Processors , IEEE ISSS+CODES, October 2003, (with H. Xie and L. Zhao).

Network I/O Architectures:

A New Server I/O Architecture for High Speed Networks , International Symposium on High-Performance Computer Architecture (HPCA), San Antonio, TX, Feb 2011 (with G. Liao and X.Zhu)
A New TCB Cache to Efficiently Manage TCP Sessions for Web Servers , ACM/IEEE Symposium on Architecture of Networks and Communication Systems (ANCS), San Diego, CA, October 2010 (with G. Liao, W. Wu and H. Yu)
Performance Measurement of an Integrated NIC Architecture with 10GbE , IEEE Hot Interconnect Symposium, Palo Alto, CA, August 2009, (with G. Liao)
Software Techniques to Improve Virtualized I/O Performance on Multi-core Systems , ACM/IEEE Symposium on Architecture of Networks and Communication Systems (ANCS), San Jose, CA, December 2008 (with G. Liao, D. Guo and S. King)
Hardware Support for Accelerating Data Movement in Server Platform , IEEE Transactions on Computers, Vol. 56, No.6, June 2007, pp. 740-753 (With L. Zhao, et.al.)
A Network Processor-Based Content Aware Switch , IEEE Micro, Special Issue on High-Performance Interconnects, May/June 2006, (with L. Zhao, et al).
Performance Characterization of a 10 Gigabit Ethernet TOE , 13th International Symposium on High Performance Interconnects (Hot-I05), Stanford, CA, August 2005, (with W. Feng, et al).
Anatomy of UDP and MVIA for Cluster Communication , Journal of Parallel and Distributed Computing, Special Issue on Cluster and Grid Computing, 2005, (with X. Zhang and W. Feng).

Multiprocessor/Cluster System:

Load Balancing in a Cluster-Based Web Server for Multimedia Applications, IEEE Transactions on Parallel and Distributed Systems, Vol. 17, No.11, November 2006 (With Jiani Guo)
Switch MSHR: A Technique to Reduce Remote read Memory Latency in CC-NUMA Multiprocessors , IEEE Transactions on Computers, May 2003, pp. 617-632,(with H. Wang).
Design and analysis of Static Memory Management Policies for CC-NUMA Multiprocessors , Journal of Systems Architecture, Elsevier Science Publication, 48 (1-3), September 2002, (with R. Iyer and H. Wang).
Comparing the Memory System Performance of DSS Workloads on the HP V-Class and SGI Origin 2000 , IEEE IPDPS, April 2002, (with R. Yu and R. Iyer).
Design and Analysis of a Switch Cache Architecture for CC-NUMA Multiprocessors, , IEEE Transactions on Computers, August 2000. (With Ravi Iyer)