Other Recent Projects:
- National Science Foundation, Principal Investigator, Scheduling in High Performance Internet Routers, Sept. 2003 through August 2008.
- Intel Corporation and UC Micro, Principal Investigator, Advanced Acceleration Solutions for Next Generation Data Center Servers, 2003-2007.
- Intel IXA University Program and UC Micro, Principal Investigator, Network Processor Architecture Laboratory , 2003-present.
- National Science Foundation, Co-Principal Investigator, Scalable Software System for Large Internet Servers, April 2003 through March 2007 (With P. Mohapatra at UC, Davis).
- National Science Foundation, Principal Investigator, ITR: Collaborative Research: Processor Architectures for Web Switches, Sept. 2002 through August 2006.
- Los Alamos National Laboratory, Principal Investigator, Interface Design for High-Performance Networking, November 2003 to June 2005, (with Mart Molle).
- National Science Foundation, Principal Investigator, High-Performance Internet Router Architectures, Sept. 2001 through August 2004.
- Intel IXA University Program and UC Micro, Principal Investigator, Design and Application of Network Processors, 2003-2004.
- National Science Foundation, Principal Investigator, High Performance Switch Architectures for CC-NUMA Multiprocessors, Sept. 1998 through Aug. 2003.
- National Science Foundation, Principal Investigator, ``Cache Coherence in Wormhole Networks,'' April 1996 through August 2001.
- Texas Advanced Technology Program, Principal Investigator, ``Architecture Evaluation using Commercial Workloads,'' Jan. 2000 through Dec. 2001.
- IBM TJ Watson Research Center, Principal Investigator, ``Research in Shared Memory Multiprocessors,'' University Partnership Award, 1998, Unrestricted.
- Texas Energy Resource Program, Co-Principal Investigator, ``Parallel Processing Algorithms for Rapid CT Scan Analysis,'' June 1998 through May 1999, (with D. Mamora).
- Hewlett-Packard Co., Principal Investigator, ``Research in Shared Memory Multiprocessors, HP V-Class 16 processor Machine,'' January 1998 through December 2000, (with N. Amato and L. Rauchwerger).
- Texas Advanced Technology Program, Principal Investigator, ``Fault Tolerance in Multiprocessor Arrays,'' Jan 1994 through August 1996, (with F. Lombardi).
- National Science Foundation, Principal Investigator, ``Cache Architecture s for Large Shared Memory Multiprocessors,'' July 1993 through June 1997.
- National Science Foundation, CISE Small Scale Institutional Infrastructure Program, Co-Principal Investigator, ``Research in Parallel and Distributed Computing,'' March 1992 through Feb 1996, (with R. Volz and U. Pooch).
- International Business Machines, Principal Investigator, ``Evaluation of Cluster Architectures,'' Jan 1993 through Dec 1993.
- Texas Advanced Technology Program, Co-Principal Investigator, ``An Approach to Solve the Cache Thrashing Problem,'' Jan 1992 through Dec 1993, (with Mi Lu).
- Texas Instruments, Principal Investigator, ``Mapping Algorithms onto Parallel Architectures,'' 1991, Unrestricted.
- National Science Foundation, Principal Investigator, ``Design and Analysis of Cache Coherence Protocols for MIN Based Multiprocessors,'' August 1990 thrugh July 1993.
Number of Publications:
- Journal Publications: 55
- Conference Proceedings: 100
- Presentations: 50
Selected Publications:
High-Performance IP Routers:
- Adaptive Max-min Fair Scheduling in Buffered Crossbar Switches Without Speedup , IEEE INFOCOM 2007, Anchorage, Alaska, May 2007 (with X. Zhang and S. Mohanty).
- EaseCAM: An Energy and Storage Efficient TCAM-Based Architecture for IP Lookup , IEEE Transactions on Computers, May 2005, pp. 521-533, (With V.C. Ravikumar and R.N. Mahaptra).
- An Efficient Scheduling Algorithm for Combined-Input-Crosspoint-Queued (CICQ) Switches , IEEE Globecom, Dallas, TX, November 2004, (With X. Zhang).
- Deficit Round Robin Scheduling for Input-queued Switches , IEEE Journal of Selected Areas in Communications, Special Issue on High Performance Optical/Electronic Switches/Routers for High Speed Internet, May 2003, pp. 584-594, (With X. Zhang).
- Shared Memory Multiprocessor Architectures for Software IP Routers, , IEEE Transactions on Parallel and Distributed Systems, Dec 2003, pp. 1240-1249, (with Yan Luo and Xi Chen)
- Fair Scheduling for Input Buffered Switches , Journal of Cluster Computing, Special Issue on Communication Architecture for Clusters, Kluwer Academic Publishers, Vol.6, No.2, April 2003. (with Nan Ni)
- A Cluster-based Active Router Supporting Video/Audio Stream Transcoding Service, IEEE IPDPS, Nice, April 2003.
- Fair Scheduling in Internet Routers , IEEE Transactions on Computers, Special Issue on Quality of Service Issues in Internet Web Services, June 2002, pp. 686-701(with N. Ni).
- Fair Scheduling and Buffer Management in Internet Routers , IEEE INFOCOM, New York, June 2002(with N. Ni).
Network Processors:
- Program Mapping onto Network Processors by Recursive Bipartitioning and Refining , 44th Design Automation Conference (DAC), San Diego, June 2007, (with Jia Yu, et al).
- A Network Processor-Based Content Aware Switch , IEEE Micro, Special Issue on High-Performance Interconnects, May/June 2006, (with L. Zhao, et al).
- Performance Characterization of a 10 Gigabit Ethernet TOE , 13th International Symposium on High Performance Interconnects (Hot-I05), Stanford, CA, August 2005, (with W. Feng, et al).
- Low Power Network Processor Design using Clock Gating , ACM Design Automation Conference (DAC), June 2005, (with Y. Luo, et al).
- Anatomy and Performance of SSL Processing , ISPASS, Austin, TX, March 2005, (with L. Zhao et al).
- An Efficient Packet Scheduling Algorithm in Network Processors , IEEE Infocom, March 2005, (with J. Guo and J. Yao).
- NePSim: A Network Processor Simulator with Power Evaluation Framework , IEEE Micro, Special Issue on Network Processors, September/October 2004, (with Y. Luo et al).
- Scheduling Real-time Multimedia Tasks in Network Processors , IEEE Globecom, Global Internet and Next Generation Systems Symposium, Dallas, November 2004, (with J. Yao et al).
- TCP/IP Cache Characterization in Commercial Server Workloads , CAECW 2004, Along with HPCA-10, February 2004, (with L. Zhao et al).
- Utilizing Formal Assertions for System Design of Network Processors , Design Forum, Design Automation and Test in Europe (DATE), 2004 (with Y. Liu et al).
- Architectural Analysis and Instruction Set Optimization for Network Protocol Processors , IEEE ISSS+CODES, October 2003, (with H. Xie and L. Zhao).
- Loop Level Analysis of Security and Network Applications , Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-03) with HPCA-9, Anaheim, CA, February 2003 (with D. Suresh et.al.).
- Architectural Analysis of Cryptogrphic Applications for Network Processors , IEEE First Workshop on Network Processors, with HPCA-8, Boston, February 2002 (with H. Xie and L. Zhou).
- Benchmarking Web Server Architectures: A Simulation Study on Micro Performance , Fifth Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-02), with HPCA-8, Boston, MA, February 2002 (with H. Xie and L. Zhou).
Switch and Cache Architectures:
- Anatomy of UDP and MVIA for Cluster Communication , Journal of Parallel and Distributed Computing, Special Issue on Cluster and Grid Computing, 2005 (in press), (with X. Zhang and W. Feng).
- Switch MSHR: A Technique to Reduce Remote read Memory Latency in CC-NUMA Multiprocessors , IEEE Transactions on Computers, May 2003, pp. 617-632,(with H. Wang).
- Design and Analysis of a Switch Cache Architecture for CC-NUMA Multiprocessors, , IEEE Transactions on Computers, August 2000. (With Ravi Iyer)
- Exploring the switch design space in a CC-NUMA multiprocessor environment , International Parallel and Distributed Processing Symposium (IPDPS 2000), Cancun, Mexico, May 2000. (with Marius Pirvu and Nan Ni)
- Impact of CC-NUMA Memory Management Policies on the Application Performance of Multistage Switching Networks, IEEE Transaction on Parallel and Distributed Systems, March 2000, pp. 230-246. (with Ravi Iyer , Hu-jun Wang and Akhilesh Kumar)
- The Impact of Link Arbitration on Switch Performance, Fifth Symposium on High performance Computer Architecture (HPCA-5), Jan 1999. (with Marius Pirvu and Nan Ni)
- An Efficient Hybrid Cache Coherence Protocol for Shared Memory Multiprocessors , IEEE Transactions on Computers, March 1999, pp.352-360 (with Y. Chang)
Multiprocessor/Cluster System:
- Hardware Support for Accelerating Data Movement in Server Platform , IEEE Transactions on Computers, Vol. 56, No.6, June 2007, pp. 740-753 (With L. Zhao, et.al.)
- Load Balancing in a Cluster-Based Web Server for Multimedia Applications, IEEE Transactions on Parallel and Distributed Systems, Vol. 17, No.11, November 2006 (With Jiani Guo)
- Design and analysis of Static Memory Management Policies for CC-NUMA Multiprocessors , Journal of Systems Architecture, Elsevier Science Publication, 48 (1-3), September 2002, (with R. Iyer and H. Wang).
- Comparing the Memory System Performance of DSS Workloads on the HP V-Class and SGI Origin 2000 , IEEE IPDPS, April 2002, (with R. Yu and R. Iyer).
- Hardware spatial forwarding for widely shared data , International Conference on Supercomputing (ICS), Santa Fe, New Mexico, May 2000. (with Marius Pirvu)
- Comparing the Memory System Performance of the HP V-Class and the SGI Origin 2000 using Microbenchmarks and Scientific Applications. , International Conference on Supercomputing'99 (with Ravi Iyer , Nancy Amato and Lawrence Rauchwerger)
Other Selected Publications:
- Performance of Multistage Bus Networks for a Distributed Shared Memory Multiprocessor, IEEE Transactions on Parallel and Distributed Systems, Jan 1997, pp. 82-95. (with Ravi Iyer, Tahsin Askar, Aswini Nanda and Mohan Kumar ).
- "Subcube Fault Tolerance in Hypercube Multiprocessors," IEEE Transactions on Computers , Sept. 1995, pp 1108-1120 (with Y.Chang).
- "Mapping Molecular Dynamics Computations onto Hypercubes," Parallel Computing , June 1995, vol. 21, pp. 993-1013 (with V. Laxamsani and D.S. Linthiam).
- "Multiprocessor Performance Measurement and Evaluation," IEEE Computer Society Tutorial, 1994.
- "Design and Analysis of Cache Coherent Multistage Interconnection Networks," IEEE Transactions on Computers , April 1993, pp. 458-470. (with A. K. Nanda)
- "Efficient Mapping of Applications for Cache-Based Multiprocessors," Journa l of Parallel and Distributed Computing, Nov. 1993 (with A. K. Nanda).
- "Design of a Dynamic Cache Coherence Protocol for Large Scale Multiprocessors, " IEEE Transactions on Parallel and Distributed Systems, May 1992 (with Q. Yang)
- "Performance Evaluation of a Dataflow Architecture,"IEEE Transactions on Computers, May 1990 (with D. Ghosal).
- "Analysis and Comparison of Cache Coherence Protocols for a Packet Switched Mult iprocessor," IEEE Transactions on Computers, Special Issue on Distributed Processing, August 1989 (with Q. Yang an d B.C. Liu).
- "Performance of Multiprocessor Interconnection Networks,"IEEE Computer, Feb. 1 989 (with Q. Yang and D.P. Agrawal).