Laxmi N. Bhuyan
Computer Science and
University of California,
Riverside, CA 92521
Office: 351, Winston Chung Hall
Phone: (951) 827-2244
Fax: (951) 827-4643
Narayan Bhuyan is Distinguished
Professor and Chairman of Computer Science and Engineering Department at
the University of California, Riverside (UCR). Prior to joining UCR in January
2001, he was a professor of Computer Science at Texas A&M University
(1989-2000) and Program Director of the Computer System Architecture Program at
the National Science Foundation (1998-2000). He has also worked as a consultant
to Intel and HP Labs.
Dr. Bhuyan received his Ph.D. degree in Computer
Engineering from Wayne State University in 1982. His current research interests
are in the areas of network packet processing, multiprocessor architectures,
network processors and I/O architectures, high-performance IP routers, parallel
and distributed processing, and performance evaluation. He has published more
than 150 papers in these areas in IEEE Transactions on Computers (TC), IEEE
Transactions on Parallel and Distributed Systems (TPDS), Journal of Parallel
and Distributed Computing (JPDC), and many refereed conference proceedings.
Dr. Bhuyan served as the Editor-in-Chief of
the IEEE Transactions on Parallel and Distributed Systems (TPDS) from 2006 to
2009. He is a past Editor of the IEEE TC, JPDC, and Parallel Computing Journal.
His professional activities are too numerous to describe. To mention a few, he
was the founding Program Committee Chairman of the HPCA in 1995, Program Chair
of the IPDPS in 1996, General Chair of ADCOM-2001, and General Chair of HPCA-9
(2003). He was elected Chair of the IEEE Computer Society Technical Committee
on Computer Architecture (TCCA) between 1995-1998.
Dr. Bhuyan is a Fellow of the IEEE, a Fellow of
the ACM, a Fellow of the AAAS (American Association for the Advancement of
Science), and a Fellow of the WIF (World Innovation Foundation). He has
also been named as an ISI Highly Cited Researcher in Computer Science.
He has received other awards such as Halliburton Professorship at Texas A&M
University, and Senior Fellow of the Texas Engineering Experiment Station. He
was also awarded the IEEE CS Outstanding Contribution Award in 1997. He was
inducted into the Distinguished Alumni Hall of Fame of the Wayne State
University College of Engineering in October 2010. He received the Distinguished
Alumnus Award from National Institute of Technology, Rourkela in 2011.
Computer Engineering, Wayne State University, 1982
M.Sc. Electrical Engineering, REC, Rourkela, Sambalpur
B.Sc. Electrical Engineering, REC, Rourkela, Sambalpur
- Distinguished Professor, Department of Computer Science
& Engineering, University of California at Riverside, July 2010 -
- Chairman, Department of Computer Science &
Engineering, University of California at Riverside, July 2007 - Present
- Professor, Computer Science & Engineering,
University of California at Riverside, January 2001 - Present
- Professor, Computer Science, Texas A&M University,
September 1991 - December 2000
- Program Director, Computer System Architecture, NSF,
September 1998 - August 2000
- Consultant, Hewlett Packard Laboratories, August 1998
- Consultant/Visiting Professor, Intel Corporation,
- Associate Professor, Computer Science, Texas A&M
University, August 1989-1991
- Associate Professor, The Center for Advanced Computer
Studies, University of Southwestern Louisiana, 1985-August 1989
- Assistant Professor, Electrical and Computer
Engineering, University of Southwestern Louisiana, 1983-1985
- Assistant Professor, Electrical Engineering, University
of Manitoba, 1982-1983
- Dr. Chita R. Das , 1986, Distinguished
Professor, Pennsylvania State University
- Dr. Qing Yang ,
1988, Distinguished Engineering Professor, University of Rhode
- Dr. Dipak Ghosal , 1988,
University of California at Davis
- Dr. Hong Jiang , 1991, University
- Dr. Ashwini Nanda , 1993, IBM TJ Watson Research
- Dr. C.H. Chen, 1993, University of Tuskegee
- Dr. Jason Ding , 1994,
- Dr. Yeimkuan Chang, 1995,
Chung-Hua Polytechnic Institute
- Dr. Phanindra
Mannava, 1995, Intel Corporation
- Dr. Chao Feng, 1995, Cisco
- Dr. Akhilesh
Kumar , 1996, Intel Corporation
- Dr. Ravi Iyer , 1999, Intel Corporation
- Dr. Marius Pirvu , 2000, Compaq Corporation
- Dr. Nan Ni ,
2000, IBM Corporation
- Dr. Hu-Jun Wang , 2001, IBM Corporation
- Dr. Yan Luo , 2005, University of Massachusetts at Lowell
- Dr. Xiao Zhang ,
- Dr. Li Zhao ,
2005, Intel Corporation
- Dr. Jiani Guo , 2006, Cisco
- Dr. Satya Mohanty , 2007,
- Dr. Jingnan Yao , 2007, Cisco
- Dr. Jia Yu , 2007, VMWare
- Dr. Anirban Banerji , 2009,
- Dr. Danhua Guo , 2010,
- Dr. Guangdeng Liao , 2011, Intel Research
- Dr. Jilong Kuang , 2011,
- Dr. Yi Hu, 2012
- Past/Current Research Associates
- Dr. Rabi Mahapatra
, 1997 From IIT, Kharagpur
- Dr. Yeimkuan Chang , 2001 From Taiwan National
- Dr. Zhiyong Xu , From University of Cincinnati
- Dr. In - Bum Jung , 2003 From
- Dr. Bin Liu , 2006, From Tshinghua University
- Dr. Heeyeol Yu
, 2009, From Texas A&M University
- Dr. Qin Liu, 20, From Wuhan
Current Ph.D. Students:
- Chih-hsun Chou
- Frank Yang
- Dong Vu
- M.S. Graduates: 30
- Distinguished Alumnus Award,
Hall of Fame, Wayne State University, COE, 2010
Alumnus Award, NIT, Rourkela, 2011
- ISI Highly
Cited Researcher in Computer Science
- Fellow of
- Fellow of
- Fellow of
- Fellow of
the World Innovation Foundation (WIF)
Senior Specialist Award, 2004
- IBM University
Partnership Award, 1998
Core Member, IEEE Computer Society, 1997
Contribution Award, IEEE Computer Society, 1996
Fellow Award, Texas Engineering Experiment Station (TEES), 1996
Professorship Award, 1991
Fellow Award, 1992, 1994
Selected Professional Activities:
IEEE Transactions on Parallel and Distributed Systems, January 2006-2009
Editor, IEEE Trandactions on Computers,
Journal of Parallel and Distributed Computing, 1995-2006
Board, Parallel Computing, 1992-2006
Co-Chairman, IEEE Int. Symposium on High-Performance Computer Architecture
(HPCA9), Feb 2003
IEEE Computer Society Technical Committee on Computer Architecture (TCCA),
Editor, IEEE Transactions on Parallel and Distributed Systems, 1998-1999
- Editor -
System Architecture, IEEE Computer Magazine, 1991- 1997
Co-Chairman, International Symposium on Parallel and Distributed
Processing (SPDP), 1996
Chairman, International Symposium on High-Performance Computer
Architectures (HPCA), 1995
Lecturer, 1991- 1995
Visitor, IEEE Computer Society, 1987-1990
Interests and Areas of Expertise:
Packet Processing and I/O architectures
- P2P and
Router and Web Server Architectures
and Distributed Systems
Science Foundation, Principal Investigator, Power
Efficient Multicore Scheduling of Network Applications, October 2012
through September 2015.
Science Foundation, Principal Investigator, (Co-PI: Rajiv Gupta) EAGER: Developing a Programming Environment for
Heterogeneous Multiprocessors, September 2012 through August 2014.
Science Foundation, Principal Investigator, (Co-PIs: Rajiv Gupta and Walid Najjar) SHF: Medium: Hardware/Software Partitioning for
Hybrid Shared Memory Multiprocessors, September 2009 through August
Science Foundation, Principal Investigator, CSR:
Small: Core Scheduling to Improve Virtualized I/O Performance on
Multi-Core Systems, September 2009 through August 2012.
Science Foundation, Principal Investigator, Virtualizaion-Aware Architectures to Accelerate Netwok I/O Processing, September 2008 through
Science Foundation, Principal Investigator, Application
Oriented Edge Router, September 2008 through August 2012.
Corporation, CPU+NIC Architectures to Accelerate
I/O Processing, July 2007 through June 2010.
Principal Investigator, Intelligent Message
Scheduling on Application Oriented Networking (AON) System, 2006,
Other Recent Projects:
Science Foundation, Principal Investigator, Software
Architectures for Distributed Web Services Based on Peer-to-Peer
Technologies, October 2005 through September 2009.
Science Foundation, Principal Investigator, Acquisition
of an Ultra Low-Latency Multiprocessor System with On-Board Hardware
Accelerator, August 2006 through July 2009.
Science Foundation, Principal Investigator, Scheduling in High Performance
Internet Routers, Sept. 2003 through August 2008.
Corporation and UC Micro, Principal Investigator, Advanced Acceleration Solutions for Next
Generation Data Center Servers, 2003-2007.
- Intel IXA
University Program and UC Micro, Principal Investigator, Network Processor Architecture Laboratory ,
Science Foundation, Co-Principal Investigator, Scalable Software System
for Large Internet Servers, April 2003 through March 2007 (With P. Mohapatra at UC, Davis).
Science Foundation, Principal Investigator, ITR: Collaborative Research:
Processor Architectures for Web Switches, Sept. 2002 through August 2006.
- Los Alamos
National Laboratory, Principal Investigator, Interface Design for
High-Performance Networking, November 2003 to June 2005, (with Mart Molle).
Science Foundation, Principal Investigator, High-Performance Internet
Router Architectures, Sept. 2001 through August 2004.
- Intel IXA
University Program and UC Micro, Principal Investigator, Design and
Application of Network Processors, 2003-2004.
Science Foundation, Principal Investigator, High Performance Switch
Architectures for CC-NUMA Multiprocessors, Sept. 1998 through Aug. 2003.
- National Science
Foundation, Principal Investigator, ``Cache Coherence in Wormhole
Networks,'' April 1996 through August 2001.
Advanced Technology Program, Principal Investigator, ``Architecture
Evaluation using Commercial Workloads,'' Jan. 2000 through Dec. 2001.
- IBM TJ
Watson Research Center, Principal Investigator, ``Research in Shared
Memory Multiprocessors,'' University Partnership Award, 1998,
Energy Resource Program, Co-Principal Investigator, ``Parallel Processing Algorithms
for Rapid CT Scan Analysis,'' June 1998 through May 1999, (with D. Mamora).
Co., Principal Investigator, ``Research in Shared Memory Multiprocessors,
HP V-Class 16 processor Machine,'' January 1998 through December 2000,
(with N. Amato and L. Rauchwerger).
Advanced Technology Program, Principal Investigator, ``Fault Tolerance in
Multiprocessor Arrays,'' Jan 1994 through August 1996, (with F. Lombardi).
Science Foundation, Principal Investigator, ``Cache Architecture s for
Large Shared Memory Multiprocessors,'' July 1993 through June 1997.
Science Foundation, CISE Small Scale Institutional Infrastructure Program,
Co-Principal Investigator, ``Research in Parallel and Distributed
Computing,'' March 1992 through Feb 1996, (with R. Volz
and U. Pooch).
Business Machines, Principal Investigator, ``Evaluation of Cluster
Architectures,'' Jan 1993 through Dec 1993.
Advanced Technology Program, Co-Principal Investigator, ``An Approach to
Solve the Cache Thrashing Problem,'' Jan 1992 through Dec 1993, (with Mi
Instruments, Principal Investigator, ``Mapping Algorithms onto Parallel
Architectures,'' 1991, Unrestricted.
Science Foundation, Principal Investigator, ``Design and Analysis of
Cache Coherence Protocols for MIN Based Multiprocessors,'' August 1990 thrugh July 1993.
- Journal Publications: 65
- Conference Proceedings: 130
- Presentations: 50
High-Performance IP Routers:
- A New IP Lookup Cache for High
Performance IP Routers , ACM Design Automation Conference (DAC),
Anaheim, June 2010 (with G. Liao and H. Yi).
hash-based scalable IP lookup using Bloom and fingerprint filters,
IEEE ICNP 2009, Princeton, NJ, October 2009 (with H. Yu and R. Mahapatra).
- Adaptive Max-min Fair Scheduling in Buffered
Crossbar Switches Without Speedup , IEEE INFOCOM 2007, Anchorage,
Alaska, May 2007 (with X. Zhang and S. Mohanty).
- EaseCAM: An Energy
and Storage Efficient TCAM-Based Architecture for IP Lookup , IEEE
Transactions on Computers, May 2005, pp. 521-533, (With V.C. Ravikumar and R.N. Mahaptra).
- An Efficient Scheduling Algorithm for
Switches , IEEE Globecom, Dallas, TX,
November 2004, (With X. Zhang).
- Deficit Round Robin Scheduling for
Input-queued Switches , IEEE Journal of Selected Areas in
Communications, Special Issue on High Performance Optical/Electronic
Switches/Routers, May 2003, (with X. Zhang).
- Shared Memory Multiprocessor Architectures for
Software IP Routers, , IEEE Transactions on Parallel and Distributed
Systems, Dec 2003, pp. 1240-1249, (with Yan Luo
and Xi Chen)
- Fair Scheduling for Input Buffered Switches ,
Journal of Cluster Computing, Special Issue on Communication Architecture
for Clusters, Kluwer Academic Publishers,
Vol.6, No.2, April 2003. (with Nan Ni)
- A Cluster-based Active Router Supporting
Video/Audio Stream Transcoding Service,
IEEE IPDPS, Nice, April 2003.
- Fair Scheduling in Internet Routers , IEEE
Transactions on Computers, Special Issue on Quality of Service Issues in
Internet Web Services, June 2002, pp. 686-701(with N. Ni).
Network Packet Processing:
- An Efficient Parallelized
L7-Filter Design for Multicore Servers, IEEE/ACM Transactions on
Networking, October 2012 (with D. Guo and B.
- Traffic-aware Power Optimization for Network
Applications on Multicore Servers, ACM Design Automation Conference
(DAC), San Francisco, June 2012 (with J. Kuang
and R. Klefstad)
- A QoS Aware
Multicore Hash Scheduler for Network Applications , IEEE INFOCOM,
Shanghai, China, April 2011 (with D. Guo).
- LATA: A Latency and Throughput-Aware Packet
Processing System , ACM Design Automation Conference (DAC), Anaheim,
June 2010 (with J. Kuang).
- Optimizing Throughput and Latency under
Given Power Budget for Network Packet Processing , IEEE INFOCOM, San
Diego, CA, March 2010 (with J. Kuang).
- Ordered Round Robin: An Efficient Sequence
Preserving Scheduler for Network Processors , IEEE Transactions on
Computers, December 2008, pp. 1690-1703 (with J. Yao and J. Guo).
- Quantum-Adaptive Scheduling for Multi-Core
Network Processors , International Conference on Distributed
Computing Systems (ICDCS), June 2008, Beijing, China (with Y. Zhang et
- Program Mapping onto Network Processors by
Recursive Bipartitioning and Refining , 44th
Design Automation Conference (DAC), San Diego, June 2007, (with Jia Yu, et al).
- Low Power Network Processor Design using Clock
Gating , ACM Design Automation Conference (DAC), June 2005, (with Y. Luo, et al).
- An Efficient Packet Scheduling Algorithm in
Network Processors , IEEE Infocom, March
2005, (with J. Guo and J. Yao).
- NePSim: A Network
Processor Simulator with Power Evaluation Framework , IEEE Micro,
Special Issue on Network Processors, September/October 2004, (with Y. Luo et al).
Network I/O Architectures:
Performance and Power Efficiency of Network Processing over 10GbE, Journal of Parallel and
Distributed Computing (JPDC), Special Issue on Communication
Architectures for Scalable Systems, To appear
New Server I/O Architecture for High Speed Networks , International
Symposium on High-Performance Computer Architecture (HPCA), San Antonio,
TX, Feb 2011 (with G. Liao and X.Zhu)
- A New TCB Cache to Efficiently Manage TCP
Sessions for Web Servers , ACM/IEEE Symposium on Architecture of
Networks and Communication Systems (ANCS), San Diego, CA, October 2010
(with G. Liao, W. Wu and H. Yu)
- Performance Measurement of an Integrated NIC
Architecture with 10GbE , IEEE Hot Interconnect Symposium, Palo Alto,
CA, August 2009, (with G. Liao)
- Software Techniques to Improve Virtualized
I/O Performance on Multi-core Systems , ACM/IEEE Symposium on
Architecture of Networks and Communication Systems (ANCS), December 2008
(with G. Liao, D. Guo and S. King)
- Hardware Support for Accelerating Data Movement in
Server Platform , IEEE Transactions on Computers, Vol. 56, No.6, June
2007, pp. 740-753 (With L. Zhao, et.al.)
- A Network Processor-Based Content Aware
Switch , IEEE Micro, Special Issue on High-Performance Interconnects,
May/June 2006, (with L. Zhao, et al).
- Performance Characterization of a 10 Gigabit
Ethernet TOE , 13th International Symposium on High Performance Interconnects
(Hot-I05), Stanford, CA, August 2005, (with W. Feng,
- Anatomy of UDP and MVIA for Cluster
Communication , Journal of Parallel and Distributed Computing,
Special Issue on Cluster and Grid Computing, 2005, (with X. Zhang and W. Feng).
Data Consistency in Structured P2P Systems, IEEE Transactions on
Parallel and Distributed Systems (TPDS), (with Y. Hu
and M. Feng) To appear
- ADAPT: A Framework for Coscheduling Multithreaded Programs, ACM Transactions on Architecture
and Code Optimization (TACO),
January 2013 (with K Pusukuri
and R. Gupta)
Consistency Support for Large-Scale Interactive Applications,
Computer Network (COMNET), The International Journal of Computer and
Telecommunications Networking, April 2012, (with Yi Hu
- Thread Tranquilizer: Dynamically
Reducing Performance Variation, ACM Transactions on Architecture and
Code Optimization (TACO),
January 2012 (with K Pusukuri
and R. Gupta)
- No More Backstabbing... A Faithful
Scheduling Policy for Multithreaded Programs, Parallel Architectures
and Compilation Techniques (PACT), October 2011 (with K. Pusukuri, R. Gupta)
- Load Balancing in a Cluster-Based Web Server for
Multimedia Applications, IEEE Transactions on Parallel and
Distributed Systems, Vol. 17, No.11, November 2006 (With Jiani Guo)
- Switch MSHR: A Technique to Reduce Remote read
Memory Latency in CC-NUMA Multiprocessors , IEEE Transactions on
Computers, May 2003, pp. 617-632,(with H. Wang).
- Design and analysis of Static Memory Management
Policies for CC-NUMA Multiprocessors , Journal of Systems
Architecture, Elsevier Science Publication, 48 (1-3), September 2002,
(with R. Iyer and H. Wang).