EE 190 / CS 193 Undergraduate Research Projects - Spring 2021

Course Information

  • Time and Location:
    Weekly Meetings: Fri 12:00pm - 2:00pm @ online zoom meeting
  • Instructor: Marcus Chow


Welcome to Undergraduate Research!

Class Syllabus

Class webpage and Communication

The class webpage is located at

Information, resources, and announcements related to the class will be posted to the webpage.

Course Description

This Design Project course will focus on the development and evaluation of Basic Linear Algebra Subroutine (BLAS) Libraries on several parallel computing architectures. Specifically, this project will utilize Nvidia’s Jetson Nano, AMD GPU's, the Raspberry Pi, and Bespoke Silicon Group’s Manycore processor. The goal of this project is to survey each system for its performance and power consumption in order to explore potential energy-efficiency benefits. This will enable accessible, energy efficient embedded systems to perform computationally complex functions, while being able to scale both utilization and power consumption proportionally

Course Outcomes

  • Learn the principles of modern Parallel Architectures
  • Gain experience in software development of large open-source projects that are currently deployed in industry.
  • Develop Parallel Algorithms and learn how to conduct performance and energy evaluations on them.
  • Gain experience in Computer Engineering Research

Grade Breakdown

  • Weekly progress reports: 30%
  • Project Implementation 30%
  • Project Presentation: 10%
  • Project demonstration: 10%
  • Project report: 20%
  • Class Participation & Discussion: 10%
Letter Grade Percentage
A > 93%
A- > 90%
B+ > 87%
B > 83%
B- > 80%
C+ > 77%
C > 73%
C- > 70%

Online Attendence Policies

  • You are expected to attend all Weekly Meetings. You participation is vital in cultavativing an effective learning envirnment.
  • For online lecture you must have an available camera and microphone. I execpt everyone to turn on the camera during the lecture and be open for discussion. My goal is to treat our online course as much as an in person classroom as possible.

Academic Accommodations

If you have a disability or believe you may have a disability, you can arrange for accommodations by contacting Services for Students with Disabilities (SSD) at 951-827-4538 (voice) or (email). Students needing academic accommodations must first register with SSD and provide required disability-related documentation. If you already have approved accommodation(s), you are advised to notify the faculty instructor of record for this course privately.

Academic Rights

All students, faculty, and staff are responsible for understanding and complying with the University’s stated academic requirements. Students should feel free to express their thoughts and opinions in an academic forum.

Academic Integrity

Here at UCR we are committed to upholding and promoting the values of the Tartan Soul: Integrity, Accountability, Excellence, and Respect. As a student in this class, it is your responsibility to act in accordance with these values by completing all assignments in the manner described, and by informing the instructor of suspected acts of academic misconduct by your peers. By doing so, you will not only affirm your own integrity, but also the integrity of the intellectual work of this University, and the degree which it represents. Should you choose to commit academic misconduct in this class, you will be held accountable according to the policies set forth by the University, and will incur appropriate consequences both in this class and from Student Conduct and Academic Integrity Programs. For more information regarding University policy and its enforcement, please visit:

Research Projects

Workloads for HammerBlade Manycore Architecture

Ana Cardenas Beltran

HammerBlade is Single-Program, Multiple-Data (SMPD) architecture. It is architected from an array of tiles that are interconnected by the manycore accelerator network. HammerBlade is a new architecture tshat we have never dealt with, so our goal for the Spring 2021 quarter is to understand the HammerBlade’s architecture and learn how to program using CUDA-Lite. While we did have experience with programming in C/C++ and a few other languages when we were first introduced to CUDA-Lite, we did not have much experience with the Linux OS, using the command line, or using text editors like VIM. So far, we have been able to complete setting up the environment for simulating the HammerBlade and have successfully run a program. Currently, we are working on learning the CUDA-Lite syntax and programming the transpose of a matrix. At the same time, we are studying its architecture to gain a better understanding of how it is programmed. The work unit of HammerBlade CUDA-Lite is the Tile Group. It is difficult to understand how to program the HammerBlade without having a prior understanding of how its architecture functions. This quarter will be spent learning how to build basic programs in CUDA-Lite and understanding the architecture of the HammerBlade. In the future, we’d like to study more of the properties of the Hammerblade, such as its energy efficiency.

BLAS Libraries for Raspberry Pi Quad Processing Unit

Emily Romero, Kashyap Panda, Nicole Garcia

Enhancing performance and making technology cost effective is a critical objective that many aim to achieve. The Raspberry Pi is an accessable, lost cost computer but lacks signifcant computaional power. Our team's goal is to optimize computation utilizing the Raspberry Pi Quad Processing Unit (QPU). We will be comparing the cost and energy efficiency of the Raspberry Pi’s QPU by developing optimized BLAS libraries. Overall, our main objective is to create embedded systems that are price accessible and that have high performance rates.

DVFS in Heterogenous Embedded Systems

Emerson Jacobson

With embedded applications running services, such as neural networks, embed boards such as Nvidia’s Jetson lineup are able to offer a good performance-per-watt metric. With the need for low power consumption, being able to scale the frequency to best match the current load should be able to offer a lower power consumption. We can measure the impact that GPU Dynamic Frequency and Voltage Scaling (DVFS) can have on power consumption by scaling resources based on the current system load. Being able to run applications on the minimum power while maintaining a Quality of Service requirement can lead to extended service when power is supplied by a finite source. The goal of this research is to create a DVFS Service that can run alongside applications and scale the CPU, GPU, and other accelerators to an appropriate level based on the current system usage. This would allow for an overall decrease in power consumption, leading to longer operation.

Tentative Schedule

The following schedule is tentative and is subject to change.

Week Date Presenter Topic Slides
1 March 29 Daniel Wong Welcome to Research!

2 April 5 Marcus Chow Introduction to Parallel Architectures Parallel_Computer_Architectures.pdf

3 April 16 Emerson Jacoboson Dynamic Voltage and Frequency Scaling on Embedded Systems DVFS.pdf

4 April 23 Kiran Ranganath Multi-Accelerator Systems MultiAccelerator_Systems.pdf

5 April 30 AmirAli Abdolrashidi Data Dependency in GPUs GPU_Data_Dependecy.pdf

6 May 7 Ana Cardenas Beltran Hammerblade Manycore Hammerblade_Manycore.pdf

7 May 14 Emily,Kashyap,Nikole BLAS for Raspberry Pi QPU Raspberry_Pi_QPU.pdf

8 May 21 Bobby, Mika GPU Tasking

9 May 28 Vahagn Tovmasian CU Scaling

10 June 4

Finals June 11