Rajiv Gupta is a Distinguished Professor and the Amrik Singh Poonian Chair in Computer Science at UC Riverside where he is a member of the RIPLE research group. His research interests include: Programming, Compiler, Runtime & Architectural Support for Parallel & Distributed Heterogeneous Systems; and Software Tools for Monitoring and Managing Runtime Behavior. He has coauthored 313 papers with an h-index of 65 and over 14,600 citations. He is a coinventor of 9 US patents. Rajiv has supervised PhD dissertations of 34 students including two winners of the ACM SIGPLAN Outstanding Doctoral Dissertation Award in Programming Languages -- (2009) Xiangyu Zhang, Purdue Univ. and (2001) Rastislav Bodik, Univ. of Washington. Five of his advisees are recipients of the NSF CAREER Award. Papers coauthored by Rajiv with his students have been selected for: inclusion in 20 Years of PLDI (1979-1999), SIGSOFT distinguished paper award in ICSE 2003, best paper award in PACT 2010, best paper award in HiPC 2020, best student paper award in LCPC 2015, the most original paper award in ICPP 2003, and outstanding paper award in ICECCS 1996. He received the UCR Doctoral Dissertation Advisor/Mentor Award (2012).

Rajiv is a Fellow of the ACM (2009), the IEEE (2008), and the AAAS (2011). He is a recipient of the NSF's Presidential Young Investigator Award (1991). Rajiv served on the Technical Advisory Group on Networking and Information Technology created by the US President's Council of Advisors on Science and Technology (PCAST) during its review of the Federal NITRD Program (2006-2007). He served as the Conference Chair for FCRC 2015; General Chair for PPoPP'20, ASPLOS'11 and PLDI'08 conferences; and Co-General Chair for CGO'05 conference. He also served as the Program Chair for PLDI'03, HPCA'03, LCTES'05, and CC'10 conferences; Program Co-Chair for CC'21 and HiPEAC'08 conferences; and Program Vice-Chair for HiPC'03 conference. Rajiv has served on program committees of major conferences in PL/Compilers & Computer Architecture including PLDI, POPL, PPoPP, CGO, ISCA, ASPLOS, MICRO, HPCA, ICS, ICDCS, PACT & HiPEAC. He served as an Associate Editor for ACM TACO & IEEE TC, and is currently serving on the boards of Parallel Computing & Computer Languages journals.

Current Projects

o   G R A S P ~~ Graph Analytics with Scalability & Performance   
o   Understanding & Managing the Dynamic Behavior of Parallel Programs  

Past Projects

o   S p i c e C ~~ Software Speculation for Irregular Parallelism  
o   Dynamic Program Analysis for Secure & Reliable Computing
o   Compiler Optimizations & Architectural Support                       

Publications, Patents & Funding

o   Complete List  ⇄  in Selected Areas  ⇄  Patents  ⇄  Funding
o   MICRO Hall of Fame  ⇄  ASPLOS Hall of Fame

	GRAPH ANALYTICS & OTHER IRREGULAR COMPUTATIONS
MICRO 2021 |78|	JetStream: Graph Analytics on Streaming Data with Event-Driven Hardware Accelerator
EuroSys 2021 |77|	Tripoline: Generalized Incremental Graph Processing via Graph Triangle Inequality
MICRO 2020 |76|	GraphPulse: An Event-Driven Hardware Acceleratorfor Asynchronous Graph Processing
EuroSys 2020 |75|	Subway: Minimizing Data Transfer during Out-of-GPU-Memory Graph Processing
ASPLOS 2019 |74|	PnP: Pruning and Prediction for Point-To-Point Iterative Graph Analytics
ASPLOS 2017 |73|	KickStarter: Fast and Accurate Computations on Streaming Graphs via Trimmed Approximations
ASPLOS 2017 |72|	CoRAL: Confined Recovery in Distributed Asynchronous Graph Processing
USENIX ATC 2016 |71|	Load the Edges You Need: A Generic I/O Optimization for Distributive Disk-based Graph Algorithms
HPDC 2016 |70|	Efficient Processing of Large Graphs via Input Reduction
ICS 2016 |69|	CuMAS: Data Transfer Aware Multi-Application Scheduling for Shared GPUs
MICRO 2015 |68|	Efficient Warp Execution in Presence of Divergence with Collaborative Context Collection
ICS 2015 |67|	PeerWave: Exploiting Wavefront Parallelism on GPUs with Peer-SM Synchronization
HPDC 2014 |66|	CuSha: Vertex-Centric Graph Processing on GPUs   (download )
OOPSLA 2014 |65|	ASPIRE: Exploiting Asynchronous Parallelism in Iterative Algorithms using a Relaxed Consistency based DSM
	UNDERSTANDING & MANAGING THE DYNAMIC BEHAVIOR OF PARALLEL PROGRAMS
ICS 2021 |64|	DSGEN: Concolic Testing GPU Implementations of Concurrent Dynamic Data Structures
OOPSLA 2019 |63|	DProf: Distributed Profiler with Strong Guarantees
ICSE 2019 |62|	Dynamic Slicing for Android (download AndroidSlicer)
SC 2017 |61|	ParaStack: Efficient Hang Detection for MPI Programs at Large Scale
HPDC 2016 |60|	Parallel Execution Profiles
OOPSLA 2015 |59|	RAIVE: Runtime Assessment of Floating-Point Instability by Vectorization
SC 2014 |58|	Fence Scoping
ICS 2013 |57|	Address-aware Fences
ASPLOS 2012 |56|	Efficient Sequential Consistency via Conflict Ordering
PLDI 2012 |55|	Effective Parallelization of Loops in the Presence of I/O Operations
PLDI 2010 |54|	Supporting Speculative Parallelization in the Presence of Dynamic Data Structures
ISCA 2009 |53|	ECMon: Exposing Cache Events for Monitoring
MICRO 2008 |52|	Copy Or Discard Execution Model For Speculative Parallelization On Multicores
	SCALABLE DYNAMIC ANALYSIS: TRACING, SLICING, DEBUGGING & FAULT LOCALIZATION
ISSTA 2008 |51|	Fault Localization Using Value Replacement
ISSTA 2008 |50|	Dynamic Recognition of Synchronization Operations for Improved Data Race Detection
PLDI 2007 |49|	Towards Locating Execution Omission Errors
ISSTA 2007 |48|	Enabling Tracing of Long-Running Multithreaded Programs via Dynamic Execution Reduction
FSE 2006 |47|	Dynamic Slicing Long Running Programs through Execution Fast Forwarding
PLDI 2006 |46|	Pruning Dynamic Slices With Confidence
ICSE 2006 |45|	Locating Faults Through Automated Predicate Switching
ASE 2005 |44|	Locating Faulty Code Using failure-Inducing Chops
ESEC-FSE 2005 |43|	Matching Execution Histories of Program Versions
ICSE 2004 |42|	Effective Forward Computation of Dynamic Slices Using Reduced Ordered Binary Decision Diagrams
PLDI 2004 |41|	Cost Effective Dynamic Program Slicing
MICRO 2004 |40|	Whole Execution Traces
ICSE 2003 |39|	Precise Dynamic Slicing Algorithms
PLDI 2001 |38|	Timestamped Whole Program Path Representation and its Applications
FSE 1995 |37|	Hybrid Slicing: An Approach for Refining Static Slices using Dynamic Information
	SCALABLE STATIC ANALYSIS & COMPILER OPTIMIZATIONS
POPL 2003 |36|	Bitwidth Aware Global Register Allocation
PLDI 2000 |35|	ABCD: Eliminating Array Bounds Checks on Demand
PLDI 1999 |34|	Load-Reuse Analysis: Design and Evaluation
ESEC-FSE 1999 |33|	Comparison Checking: An Approach to Avoid Debugging of Optimized Code
PLDI 1998 |32|	Complete Removal of Redundant Expressions
PLDI 1997 |31|	Partial Dead Code Elimination using Slicing Transformations
PLDI 1997 |30|	Interprocedural Conditional Branch Elimination
MICRO 1997 |29|	Resource-Sensitive Profile-Directed Data Flow Analysis for Code Optimization
ESEC-FSE 1997 |28|	Refining Data Flow Information using Infeasible Paths
ICSE 1996 |27|	A Demand-Driven Analyzer for Data Flow Testing at the Integration Level
POPL 1995 |26|	Demand-Driven Computation of Interprocedural Data Flow
RTSS 1994 |25|	Busy-Idle Profiles and Compact Task Graphs
PLDI 1993 |24|	A Practical Data Flow Framework for Array Reference Analysis and its Application in Optimizations
POPL 1992 |23|	Generalized Dominators and Post-Dominators
SC 1992 |22|	Techniques for Integrating Parallelizing Transformations and Compiler Based Scheduling Methods
SC 1990 |21|	Loop Displacement: An Approach for Transforming and Scheduling Loops for Parallel Execution
SC 1990 |20|	Improving Instruction Cache Performance by Reducing Cache Pollution
RTSS 1990 |19|	Applying Compiler Techniques to Scheduling in Real Time Systems
PLDI 1990 |18|	A Fresh Look at Optimizing Array Bound Checks
PLDI 1989 |17|	Register Allocation via Clique Separators
	PROCESSOR ARCHITECTURES: EMBEDDED, VLIW, MIMD & SUPERSCALAR
MICRO 2005 |16|	Efficient Use of Invisible Registers in Thumb Code
HPCA 2005 |15|	SENSS: Security Enhancement to Symmeteric Shared Memory Multiprocessors
MICRO 2002 |14|	Energy Efficient Frequent Value Data Cache Design
ICS 2001 |13|	Load and Store Reuse Using Register File Contents
MICRO 2000 |12|	Frequent Value Compression in Data Caches
ASPLOS 2000 |11|	Frequent Value Locality and Value-Centric Data Cache Design
ISCA 1999 |10|	Value Prediction in VLIW Machines
MICRO 1999 |09|	Dynamic Memory Disambiguation in the Presence of Out-of-order Store Issuing
HPCA 1999 |08|	Global Context-based Value Prediction
HPCA 1997 |07|	Distributed Path Reservation Algorithms for Multiplexed All-Optical Interconnection Networks
SC 1996 |06|	Compiled Communication for All-Optical TDM Networks
MICRO 1992 |05|	A Shape Matching Approach for Scheduling Fine-Grained Parallelism
MICRO 1991 |04|	Executing Loops on a Fine-Grained MIMD Architecture
SC 1990 |03|	The Design of a RISC based Multiprocessor Chip
MICRO 1990 |02|	A Fine-grained MIMD Architecture based upon Register Channels
ASPLOS 1989 |01|	The Fuzzy Barrier: A Mechanism for High-Speed Synchronization of Processors