UCR EE/CS 120B: Introduction to Embedded Systems

Summer 2 2004

Lecture Schedule Lab Schedule Grades Previous course offerings Prereq: CS 120A

Overview

Embedded computing systems are found everywhere, including in cellular telephones, pagers, VCRs, camcorders, thermostats, curbside rental-car check-in devices, automated supermarket stockers, computerized inventory control devices, digital thermometers, telephone answering machines, printers, portable video games, TV set-top boxes -- the list goes on. In 1997, the average U.S. household had over 10 embedded computers, not to mention the automobile, which have 35 or more by the year 2000. Demand for embedded system designers is large, and is growing rapidly. Many technical observers believe powerful ubiquitous embedded systems will create the next big revolution, just like the Internet did in the past.

In EE/CS120B, you'll learn how to develop and program basic embedded systems. It will introduce you to a unified view of hardware and software design, mapping desired functionality to a collection of single-purpose processors (digital hardware and peripherals) and general-purpose processors (microprocessors). Students will gain experience building real digital systems using VHDL, synthesis and FPGAs (Xilinx), and programming embedded microprocessors (Intel 8051 8-bit microcontroller). The follow-up courses of CS122A and CS122B introduce you to more advanced designs and methods.

Catalog description :

EE/CS 120A. Logic Design (5) Lecture, 3 hours; laboratory, 8 hours. Prerequisite(s): CS 120A/EE 120A. Introduction to hardware and software design of digital computing systems embedded in electronic devices (such as digital cameras or portable video games). Topics include custom and programmable processor design, standard peripherals, memories, interfacing, and hardware/software tradeoffs. Laboratory involves use of synthesis tools, programmable logic, and microcontrollers and development of working embedded systems. Cross-listed with EE 120B.

Basic information

Instructor(s) : Enoch Hwang, Ph.D. (ehwang@cs.ucr.edu). Office hours: MTWR 11:10am-12:00pm Office: Bourns Hall A-259.

Lecture: Section 001: MTWR 9:40am-11:10am Olmsted Hall 1136

Labs: Section 1: MTWR 2:00pm-6:00pm Surge 173

Teaching Assistants: TA office hours:
Section 1: Som Neema (sneema@cs.ucr.edu): Time: tba in BRNHL A-216

Textbook: Embedded System Design: A Unified Hardware/Software Approach, Vahid and Givargis, Wiley & Sons, 2002, Book web page

Logic and Computer Design Fundamentals and Xilinx Student Edition 4.2 Package, 3/E , by Mano and Kime, 3rd edition

Recommended:

The Students Guide to VHDL, Peter Ashenden, Morgan Kaufmann, 1st Edition, ISBN 1558605207.
or
VHDL Design Representation and Synthesis, Gray Armstrong, Prentice Hall, Second edition, ISBN 0130216704.
or another VHDL book covering synthesis.

Some free references include: Online VHDL tutorial and Hamburg VHDL archive which include Peter Ashenden's popular VHDL Cookbook.

All students should have a basic C programming book. A good C book is The C Programming Language, Kernighan and Ritchie, Prentice Hall, ISBN 0-13-110362-8.

An 8051 microcontroller book may be helpful for the lab. A good one is The 8051 Microcontroller, by Stewart and Miao, Prentice Hall, Second edition, ISBN 0-13-531948-x.
Software: We'll be using the Keil 8051 C compiler, Philips 8051 emulators/software, the Aldec VHDL simulator, and Xilinx/Synopsys Foundation Express.

You may want to consider purchasing Aldec VHDL simulator student edition. It's an easy to use yet powerful VHDL simulator written for windows. You might also consider getting the Xilinx Student Edition Software and FPGA Board

Course grading: The course consists of 100 points:

Lecture component (65 points)
- 20 pts: Midterm
- 24 pts: Final
- 8 pts: Quizzes -- 4 @ 2 pts
- 8 pts: Homeworks -- 4 @ 2 pts
- 5 pts: In-lecture exercises
Lab component (35 points)
- 30 pts: Lab assignments
- 5 pts: In-lab practical exam(s)

Grades will be assigned using a conventional grading scale: 100-90 A, 89-80 B, 79-70 C, 69-60 D, 59-0 F. +/- grades will be given. Students are NOT competing against one another, but rather against the scale -- all students can get good grades if all do well. We may adjust ("curve") an individual assessment item if such adjusting HELPS the class.

Minimum competency requirement: We want students to master both the conceptual as well as the hands-on aspects of the course. Thus, students must receive a passing grade (60% or better) in each of the lecture component and lab component, in order to receive a passing course grade (D- or better).

Study groups: Study groups - suggest going to the Science Library to meet and study there.
Class web site: www.ilearn.ucr.edu
Enrolling in this course gives you automatic access to the UCR "ilearn" site Your login id is the name field of your ucr student email address (name@student,ucr,edu), and your initial password is your Student ID (no dashes or spaces).
Class email list: CS/EE 120B mailing List (send mail now or access the archive):
Most students will be automatically subscribed to this mailing list when enrolled in the course. However, it is up to you to ensure that you are in fact subscribed (you can go to the links above to check the subscription list).

Lecture Schedule

Subject to change as the quarter progresses.
Read the book before lecture! Reading ahead is one of the most effective ways of doing better in class -- you'll be amazed how much more useful the lectures will be. We'll follow the book closely.

(LCDF: Logic and Computer Design Fundamentals; ESD: Embedded System Design)

Week 1:
- M Introduction to embedded systems (ESD 1)
- T Combinational logic design, transistors, components (ESD 2.1, 2.2)
- Homework 1 solutions
- W Sequential logic components (ESD 2.3)
- R Sequential logic design (ESD 2.4 - 2.6)
- Quiz 1 solutions
Week 2:
- M continue
- T General-purpose processors - operation (ESD 3.1, 3.3)
- Homework 2 solutions
- W General-purpose processors - programmer's view (ESD 3.4)
- R General-purpose processors - architecture & design (ESD 3.2, 3.8)
- Quiz 2 solutions
Week 3:
- M continue
- Review
- T MIDTERM Tuesday August 10 solutions
- W Memory (ESD 5.1 - 5.5)
- R continue
- Homework 3 solutions
Week 4:
- M 8051 microcontroller, Z80, EZ80
- T Peripherals - LEDs, switches, keypad, LCD (ESD 4)
- Quiz 3 solutions
- W Peripherals - timers, counters, PWM, stepper motor (ESD 4)
- R Interfacing (ESD 6)
- Homework 4 solutions
Week 5:
- M continue
- T Putting it all together
- Quiz 4 solutions
- W continue
- R Review
FINAL:
- Final solutions

Lab schedule

Subject to change as the quarter progresses.
Read the lab overview and report format.

Week 1 (a): Lab 1
Week 1 (b): Lab 2
Week 2 (a): Lab 3
Week 2 (b): Lab 4
Week 3 (a): Lab 5
Week 3 (b): Lab 6
Week 4 (a): Lab 7
Week 4 (b): Lab 8
Week 5 (a): Lab 9

Xilinx schematic entry and simulation: Appendix A
Xilinx download to development board: Appendix B
Xilinx VHDL entry: Appendix C

General course features and policies (please read these carefully)

Material covered: You'll be responsible for learning material covered in lecture, in the textbook, and in lab. We expect you to read the textbook; lecture only emphasizes key material, but does not cover all required material alone.
Collaboration policy (TA/instructor may override for particular assignment):
- Midterm, final, quizzes, lab practical -- Obviously no collaboration
- In-lecture exercises -- Dependent on instructor instructions for particular exercise.
- Homeworks -- Collaboration strongly ENCOURAGED. Study groups are great. You should still do your own solution, and should not turn in *identical* solutions as others, but similar solutions are O.K. Remember though -- these are designed to help you on the assesment items, so relying too heavily on others will hurt you during assessment.
- Lab assignments -- Limited collaboration may be acceptable, but submissions must represent YOUR OWN original work. Sharing code or team-coding are not allowed. Copying code from ANY source (any book, current or past students, past solutions, etc.) is not allowed. Collaboration may consist of discussing the general approach to solving the problem, but should not involve communicating in code or even pseudo-code. Students may help others find bugs. Your code must be unique -- the odds of randomly obtained highly-similar code is very low. Design, like surgery or driving a car or playing golf, can only be learned by doing it yourself!
Academic dishonesty: cheating is strongly punished. Report cheating (anonymously if you wish) at: https://www.cs.ucr.edu/cheating/. Note: In some courses, we use a powerful commercial tool that automatically compares all programs (this quarter and from past quarters too), neglecting changes in variable names, spacing, etc., and detects copied code. We regularly catch several cases of copying in this course EVERY QUARTER. PLEASE, don't risk it!! A couple more notes. Be aware that a subset of exams may be photocopied, for comparison with exams submitted for regrades. Also, be aware that lying to an instructor in order to be able to make up a missed exam or in other ways to obtain a better grade can be treated as academic dishonesty. During exams, cell phones must be stored away in a place not visible (e.g., inside a backpack).
Regrade policy: regrade requests must be submitted in writing and within one week of the distribution of the graded material. Grade-database errors should also be pointed out within one week of posting.
Communicating with the instructors and TAs: when sending electronic mail to the instructors or TAs, please remember that many students have the same name, and your instructor may be teaching other courses too. So please give your full name and list the course you are referring to, and preferably include your student ID number. We prefer that you use your UCR email account so that you get used to it (remember that UCR sends many official notices now only by email). Please try to be polite and professional, and use reasonable grammar and formatting.
Cell phones: During lectures and lab sessions, please turn off your cell phone.
Lab attendance: is required for the full 3-hour lab. If you finish early, work ahead on labs, do homework, read ahead, and help others if allowed (teaching increases your own learning).
Lab enrollment : To reduce disruptions and provide for the best educational environment, all persons in lab during scheduled lab time should be formally registered in that section. In general, no swapping sections and no unregistered people in the lab are allowed, even if there are extra computers.
Homeworks and lab reports: Homeworks are due at the beginning of the class period on the due date. Lab reports are due at the beginning of the lab period on the due date. No late homeworks are accepted. Your work must be completely typeset with a word processor. Circuit diagrams can be drawn using any drawing program or by hand, but it must be very neat. Handwritten works will NOT be accepted. Lab reports must follow this format.
Late/early policy for lab assignments:
- Late penalty for lab assignments due before the midterm: 7% for 1-day late, 14% for 2-days, not accepted thereafter.
- Late penalty for lab assignments due after the midterm: 10% for 1-day late, 20% for 2-days, not accepted thereafter.
- BONUS for any lab assignment turned in EARLY: 2% for 1-day early, 4% for 2-days early, 6% for 3-days or more early.
- "Day early/late" is defined as 24 hours before/after the due time.
Time Requirements: This is a five-unit engineering course. As such, you should expect to spend 3 hours/week in lecture, 6 hours/week in lab, and 6 to 10 hours/week doing individual study (readings, homeworks, programming, lab preparation, etc) -- no exaggerating here! Please don't underestimate the time you will need to spend on this course. These are real time amounts spent by successful past students. Engineering and CS are challenging disciplines requiring extensive time to master -- it's worth it in the end (great jobs, great pay, respect, etc.), but those things don't come for free. So practice, practice, practice! Work hard in school, then reap the rewards of a great career.
Final grades: Per university policy, changes to your final grade will be made only in the event of a clerical error. Asking your instructor how far you were from a cutoff and what extra work you can do to improve the grade is not appropriate.