UNIVERSITY OF CALIFORNIA, RIVERSIDE
Department of Computer Science and Engineering
Department of Electrical Engineering
EE/CS120A - Logic Design
Spring 2003
Grades are out
Schedule: Lecture: 3/31/03 - 6/13/03 TR, 7:40AM - 9:00AM, UV THE 8.
Laboratory:
- Section 21: MW, 6:10PM - 9:00PM, BRNHL B252. TA:
Rong Wang.
- Section 22: TR, 9:10AM - 12:00PM, BRNHL B252. TA:
Weikun Guo.
- Section 23: WF, 2:10PM - 5:00PM, BRNHL B252. TA:
Xiaotao Zou.
Textbook:
Instructor: Dr. Enoch Hwang.
Office: Bourns Hall A259.
e-mail: ehwang@cs.ucr.edu.
Office hours: F 11:10am - 1:00pm.
More detail and updated information on the web at
www.cs.ucr.edu/~ehwang.
Prerequisites: CS61.
Objective: To learn the principles of digital logic design focusing on combinational logic circuits.
Computer-aided design (CAD) and engineering of digital systems.
Topics: (Numbers in parenthesis are Mano & Kime sections.)
- Introduction. Digital devices.
Integrated Circuits (ICs)
pictures
. Digital-Design Levels. CAD Tools (1).
-
Number systems, hex, decimal and binary conversions, arithmetic (+, -, *, /) in binary, negative numbers. (Will not be covered in class.) (1-2).
-
Digital circuits, simple gates (2). Adder.
- VHDL
-
Boolean Algebra and Logic Design (2).
Basic theorems, boolean functions (2-2),
minterms & maxterms (2-3),
canonical and standard forms.
Technology mapping (2-6)
- Simplification of Boolean Functions (2-4, 2-5).
n-cubes,
Karnaugh maps,
simplifying expressions.
"don't-care".
- Combinational Components.
adder/subtractor (3-8, 3-9, 3-10),
ALU (7-7),
multiplexers (mux) (3-7),
decoders (3-5),
encoders (3-6),
three-state devices (p. 296),
comparators,
shifter/rotator (7-8),
ROM (6-6),
PLA (6-7).
- Transistors
CMOS transistor implementations,
Transistors on a chip as seen through an electron microscope.
- Sequential Logic
Latches (4-2), Flip-flops (4-3), Registers (5-2).
Analysis (4-4) and
synthesis (4-5) of sequential logic.
FSM.
Datapath (7-1, 7-6, 7-9, 7-10).
Register-transfer level designs (7-2, 7-4).
- Control Unit (8-1, 8-4)
Holidays:5/26/03.
Tests: Two midterms: Tue. 4/22 and Thu. 5/15.
Final: Thursday June 12, 2003, 8:00AM - 11:00AM in UV THE 8.
Academic dishonesty: It is your responsibility to be familiar with UCR's and the department's policies on academic dishonesty.
See policy.
Cheating will be punished severely.
Grading: Homeworks 10%, Labs 30%, 2 Midterms @ 15% each, Final 30%.
You must get at least 50% or the class average on the test (whichever is smaller
) on two of the three tests to pass the course.
Grades:
Grades.
If you do not want your grades to be posted on-line, please email me to let
me know. Otherwise, I will take your inaction to mean that you have given
me the approval to post your grades on-line.
It is possible for you to have a higher overall percentage but
a lower letter grade when comparing with another student
if you did not pass at least two tests.
Homeworks:
Solutions:
Labs:
VHDL links:
Summary of VHDL commands
Complete VHDL reference guide.
VHDL Lab examples
Online VHDL tutorial
Online VHDL textbook: VHDL Cookbook
VHDL synthesis tutorial
Simple VHDL examples
More VHDL examples
Xilinx Student Edition
Free Peak VHDL simulator and synthesizer
$45 Aldec VHDL simulator and synthesizer student edition
Other related links:
74xx Datasheets
Complete IC Datasheets
Online VLSI Design Tutorial
History of the transistor
Free Acrobat reader