About Me
I am a PhD candidate under supervision of Prof. Daniel Wong, at University of California, Riverside (UCR).
I work on the intersection of machine learning systems and energy-efficient computing. I have extensive experience in designing software and hardware systems for emerging applications in diverse computational environments, ranging from embedded systems to multi-GPU systems and data centers. I am exploring system and architectural limitations of inference-intensive applications, and challenges in integrating such applications into various computing devices in production.
Recent highlights include:
Systems for ML/XR: Design, profiling, and evaluating scalability, performance bottlenecks, and energy efficiency of multi-GPU ML systems such as Computer Vision and Graphics (AR/VR) in production.
Computer Architecture: Proposed architectural solutions to enhance GPU performance.
ML Accelerators: Design and development of accelerated deep learning solutions in embedded resource-constrained environments.
Recent News
| May. 2024 | Our paper "Characterizing In-Kernel Observability of Latency-Sensitive Request-level Metrics with eBPF," has been nominated for the Best Paper Award at the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) 2024. |
| Mar. 2024 | Our paper "Characterizing In-Kernel Observability of Latency-Sensitive Request-level Metrics with eBPF," has been accepted in IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2024. |
| Aug. 2023 | Our paper "WattWiser: Power Resource-Efficient Scheduling for Multi-Model Multi-GPU Inference Servers," has been accepted in IEEE International Green and Sustainable Computing (IGSC), 2023. |
| Dec. 2022 | Our paper "KRISP: Enabling Kernel-wise Right-sizing for Spatial Partitioned GPU Inference Servers," has been accepted in IEEE International Symposium on High Performance Computer Architecture (HPCA), 2023. |
Publications
| HPCA 2023 | [1] M. Chow, A. Jahanshahi, D. Wong, "KRISP: Enabling Kernel-wise RIght-sizing for Spatial Partitioned GPU Inference Servers," in IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2023. | |
| TACO 2022 | [2] A. Jahanshahi, N. Yu, D. Wong, "PowerMorph: QoS-aware Server Power Reshaping for Data Center Regulation Service," in ACM Transactions on Architecture and Code Optimization (TACO), 2022. | |
| E2ML 2021 | [3] A. Jahanshahi, R. Sharifi, M. Rezvani, H. Z. Sabzi, "Inf4Edge: Automatic Resource-aware Generation of Energy-efficient CNN Inference Accelerator for Edge Embedded FPGAs," in IEEE Workshop on Energy-Efficient Machine Learning (E2ML), 2021. | |
| NAS 2021 | [4] H. Z. Sabzi, D. Tripathy, A. Jahanshahi, D. Wong, "ICAP: Designing Inrush Current Aware Power Gating Switch for GPGPU," in 15th IEEE International Conference on Networking, Architecture, and Storage (NAS), 2021. | |
| NAS 2021 | [5] H. Z. Sabzi, Z. Shirmohammadi, A. Jahanshahi, "Deflection-aware Routing Algorithm in Network on Chip against Soft Errors and Crosstalk Faults," in 15th IEEE International Conference on Networking, Architecture, and Storage (NAS), 2021. | |
| ISCA 2021 | [6] A. Abdolrashidi, H. A. Esfeden, A. Jahanshahi, K. Singh, N. Abu-Ghazaleh, and D. Wong, "BlockMaestro: Enabling Programmer-Transparent Task-based Execution in GPU Systems," in 48th IEEE/ACM International Symposium on Computer Architecture (ISCA), 2021. | |
| CAL 2020 | [7] A. Jahanshahi, H. Z. Sabzi, C. Lau and D. Wong, "GPU-NEST: Characterizing Energy Efficiency of Multi-GPU Inference Servers," in IEEE Computer Architecture Letters (CAL), 2020. | |
| Big Data 2019 | [8] M. Karimi, A. Jahanshahi, A. Mazloumi and H. Z. Sabzi, "Border Gateway Protocol Anomaly Detection Using Neural Network," in IEEE International Conference on Big Data (BigData), 2019. | |
| CADS 2013 | [9] A. Jahanshahi, M. K. Taram and N. Eskandari, "Blokus Duo Game on FPGA," The 17th CSI Int. Symp. Computer Architecture & Digital Systems (CADS), 2013. | |