Speculative Execution in Superscalar and VLIW Architectures
Motivation
Performance of an Ideal Superscalar
ILP in Spec95
Instruction Window Size
Memory Disambiguation for Load Speculation
Conclusions of Parallelism Study
Scalability of Issue Mechanisms
Scalability of Memory Disambiguation
Direct Wake-up Superscalar
Dependence-based Microarchitecture (DBM) - Palacharla, Jouppi and Smith
Wake-Up and Steer algorithm
An Example
Ideal Schedule
DBM’s Schedule
Direct Wake-Up
Direct Wake-Up Microarchitecture (DWM)
Wake-up Graph
DWM’s Schedule
Dynamic Memory Disambiguation
Store-set Memory Disambiguator (Chrysos and Emer)
Handling of Store Instructions
Overall Performance of DWM
Flexible Architecture Simulation Tool
Very Long Instruction Word Architectures
Value Speculation
Value Prediction in VLIW Architectures
Handling Compensation Code
Our solution
Instruction Set Extensions
Example
Example (Contd.)
Synchronization of execution engines
Experimental Framework
Execution Cycles
Execution cycles vs. mispredictions per block
Publications
Email: gupta@cs.arizona.edu
Home Page: http://www.cs.arizona.edu/people/gupta