General Chairs
Nader Bagherzadeh, Univ. of California, Irvine
Laxmi N. Bhuyan, Univ. of California, Riverside
Steering Committee
Dharma P. Agrawal, Univ. of Cincinnati
Laxmi N. Bhuyan, Univ. of California, Riverside
Yale Patt, Univ. of Texas at Austin
Jean-Luc Gaudiot, Univ. of California, Irvine
Joel Emer, Intel
David Kaeli, Northeastern Univ.
Pen-Chung Yew, Univ. of Minnesota
David Lilja, Univ. of Minnesota
Program Chair
Rajiv Gupta, Univ. of Arizona
Program Committee
Todd Austin, Univ. of Michigan
Pradip Bose, IBM
David Brooks, Harvard University
Doug Burger, Univ. of Texas at Austin
Brad Calder, Univ. of California, San Diego
Dan Connors, Univ. of Colorado
Tom Conte, NC State Univ.
Darren Cronquist, HP Labs
Chita Das, Penn State Univ.
Sandhya Dwarkadas, Univ. of Rochester
Marius Evers, AMD
Kanad Ghose, SUNY Binghamton
Antonio Gonzalez, UPC, Barcelona
James Goodman, Univ. of Wisconsin
Wei-Chung Hsu, Univ. of Minnesota
Yiming Hu, Univ. of Cincinnati
Stephen Jenks, Univ. of California, Irvine
Steve Melvin, Flowstorm
Walid Najjar, Univ. of California, Riverside
Soner Onder, Michigan Technological Univ.
Santosh Pande, Georgia Tech
Sanjay Patel, UIUC
Li-Shiuan Peh, Princeton University
Timothy Mark Pinkston, USC
Ronny Ronen, Intel, Israel
John Shen, Intel, MRL
Josep Torrellas, UIUC
Mateo Valero, UPC, Barcelona
Jie Wu, Florida Atlantic Univ.
Yuanyuan Yang, SUNY at Stony Brook
Local Arrangements Chair
Stephen Jenks, Univ. of California, Irvine
Workshop Chair
Walid Najjar, Univ. of California, Riverside
Publications Chair
Li-Shiuan Peh, Princeton University
Finance and Registration Chairs
Nayla Nassif, Univ. of California, Irvine
Tony Givargis, Univ. of California, Irvine
Publicity Chair
Soner Onder, Michigan Technological Univ.
|
The International Symposium
on High-Performance Computer Architecture provides a high quality forum for
scientists and engineers to present their latest research findings in this
rapidly changing field. Authors are invited to submit full papers on all
aspects of high-performance computer architecture. Topics of interest include,
but are not limited to:
- Processor architectures
- Cache and memory architectures
- Parallel computer architectures
- Impact of VLSI scaling
techniques
- Novel architectures
for emerging applications
- Power-efficient architectures
- High-availability architectures
- High-performance I/O
architectures
- Embedded and reconfigurable
architectures
- Real-time architectures
- Interconnection networks
and network interfaces
- Innovative hardware/software
trade-offs
- Simulation and performance
evaluation
- Benchmarking and measurements
Please check the following
web site for paper submission information:
http://www.cs.arizona.edu/hpca9/
The submission should not
exceed 12 pages in IEEE double column format. Papers that exceed the length limit or that cannot be
viewed using Adobe Acrobat Reader (version 3.0 or higher) may not be reviewed.
The official submission deadline is July 12, 2002 (9pm Pacific Time, USA)
. An automatic extension of one week will be given without request. No
further extensions will be given. Papers may be submitted for blind review
at the option of the authors. Please indicate whether the paper is a student
paper for best student paper nominations. Please submit proposals for
workshops to the workshops chair by July 12, 2002. Important Dates
Paper submission
deadline: |
July
12, 2002 |
Workshop
proposals due: |
July
12, 2002 |
Author Notification:
|
Oct.
1, 2002 |
Camera ready copy
due: |
Oct.
28, 2002 |
|