CS 161 Design and Architecture of Computer Systems
Instructor: Elaheh Sadredini
Email: elaheh@cs.ucr.edu
Instructor office hours: See course calendar below
TA: Sahar Ghoflsaz, Email: sghof001@ucr.edu
TA office hours: See course calendar below
Graders:
- TBA
Discussion sessions: See course calendar below
Location of class and discussion sessions can be found here.
Discussion Forum: Link can be found on Canvas
Course Overview
Ever wondered what happens under the hood when you run a program? This course explores how computers are designed, from the hardware that executes instructions to the architectural decisions that make programs run faster. You’ll learn how software and hardware work together, and how performance, efficiency, and design trade-offs shape the computing systems we use every day.
Learning objectives:
- Understand the functionality and operation of the basic elements of a computer system including processor, memory and input/output
- Reason about first-order performance
- Understand the hardware/software interface
Course Prerequisite(s)
CS 120A / EE 120A
Textbook and Reading Material
The textbook and reading material are optional, and may be helpful supplement to the material covered in the lectures and assignments.
- Patterson & Hennessy, Computer Organization and Design: The Hardware/Software Interface, 5th Edition
- Reading material will be available on Canvas
Discussion Forum
We will be using Slack as our class forum, and our primary way of communication outside of class. For group-specific questions or private questions, you can email me.
Grading and Policies
Grading Breakdown (Total 100%)
- Homework assignments: 30% (HW0: 2%, HW2-Hw9: each 4%, one homeworks with lowest score will be dropped)
- Lab assignemnts: 40%
- Mini video to teach a concept in computer architecture: 20%
- In-class activities: 10%
Class Policies
Late submission: We do not accept any late submission for the exams. Homework assignments incur a 5% penalty per hour if submitted late, up to a maximum of 10 hours. You are allowed to skip one homework assignment without penalty—use this freebie wisely. If you choose to submit all homework assignments, your lowest score will be dropped at the end of the quarter.
Cheating policy: Collaborating with others on assignments is a valuable way to deepen your understanding and is encouraged, within clear boundaries. You may discuss the meaning of homework problems and general strategies for solving them with classmates. However, all written work and final solutions must be your own and completed individually. You may not copy from another student, share your written solutions, or use external sources such as online repositories or previous students' work in a way that substitutes for your own reasoning. Likewise, you may not allow others to copy your work.
AI tools such as ChatGPT may be used only to support your learning, such as helping you understand concepts or clarify doubts. Never use AI tools to complete assignments on your behalf. All submitted work must reflect your own thinking and understanding. Submitting AI-generated responses, even if edited, is not permitted. Any use of AI that bypasses your own effort and reasoning will be treated as academic dishonesty and result in a failing grade in the course.
Errors in grading: If you feel there has been an error in how an assignment or test was graded, you have one week from when the assignment is returned to bring it to our attention. You must submit (via email to the instructor AND the graders) a written description of the problem. Neither I nor the graders will discuss regrades without receiving an email from you about it first.
Submissions: Please ensure your files are accessible and not corrupted. Submissions that cannot be opened or read will not be accepted. Please make sure to upload the correct file. Wrong file submission, missing files, etc. requests will not be considered.
Solutions: The solutions to the homework assignments and exams will be discussed in the discussion sessions.
Grades: Your score will be available on Canvas.
Grading Scale
A+: 97 and above
A: 94-96.9
A-: 90-93.9
B+: 87-89.9
B: 84-86.9
B-: 80-83.9
C+: 77-79.9
C: 74-76.9
C-: 70-73.9
D+: 67-69.9
D: 64-66.9
D-: 60-63.9
F: Below 60
Academic Integrity
Here at UCR we are committed to upholding and promoting the values of the Tartan Soul: Integrity, Accountability, Excellence, and Respect. As a student in this class, it is your responsibility to act in accordance with these values by completing all assignments in the manner described, and by informing the instructor of suspected acts of academic misconduct by your peers. By doing so, you will not only affirm your own integrity, but also the integrity of the intellectual work of this University, and the degree which it represents. Should you choose to commit academic misconduct in this class, you will be held accountable according to the policies set forth by the University, and will incur appropriate consequences both in this class and from Student Conduct and Academic Integrity Programs. For more information regarding University policy and its enforcement, please visit: http://conduct.ucr.edu.
Student Resources
◆ If you need special accomodation, please either contact me or find more information here: "UCR campus resources"
Course Schedule
- The following schedule is tentative and is subject to change.
- Course content are posted in Canvas.
NOTE : Exact date and time for HW release, HW due, and Exam should be check on Canvas (this schedule only show the week each HW or exam is released/due, not the exact day of the week).
Week | Topic | Reading | Assignment Release | Assignment Due | Lab |
---|---|---|---|---|---|
1 | Introduction & Fundamental Concepts | Ch 1 | HW0 Release (Self Introduction) | ||
2 | Instruction Set Architecture 1 | Ch 2 | HW1 Release (ISA1) | HW0 Due | |
3 | Instruction Set Architecture 2 | Ch 2 | HW2 Release (ISA2) | HW1 Due | |
4 | Arithmetic & Logic | Ch 3 & Ch 4.1-4.2 | HW3 Release (Arithmetic/Logic) | HW2 Due | |
5 | Processor Control and Datapath | Ch 4.3-4.4 | HW4 Release (Control/Datapath) | HW3 Due | |
6 | Processor Pipelining | Ch 4.5-4.6 | HW5 Release (Pipelinig) | HW4 Due | |
7 | Pipeline Hazards | Ch 4.7-4.9 | HW6 Release (Pipeline Hazards) | HW5 Due | |
8 | Caches | Ch 5.3-5.4 | HW7 Release (Caches) | HW6 Due | |
9 | Virtual Memory | Ch 5.7 | HW8 Release (Virtual Memory | HW7 Due | |
10 | Virtual Memory and Review | Ch 5.7 | HW8 Due | ||
11 |