CS 161 Design and Architecture of Computer Systems, Winter 2024


Instructor: Elaheh Sadredini
Email: elaheh@cs.ucr.edu
Instructor office hours: See course calendar below

TA1: Jingyao Zhang, Email: jzhan502@ucr.edu
TA2: Sahar Ghoflsaz, Email: sghof001@ucr.edu
TA office hours: See course calendar below

Graders:
- Jason Sadler, Email: jsadl003@ucr.edu

Discussion sessions: See course calendar below


Location of class and discussion sessions can be found here.



Discussion Forum: Piazza (link can be found on Canvas)




Course Overview

This course will provide an introduction to the design of computer archtiecture. It covers the technical foundation of how a computing platform is designed, how software and hardware interact, and how hardware makes programs execute faster.

Learning objectives:
- Understand the functionality and operation of the basic elements of a computer system including processor, memory and input/output
- Reason about first-order performance
- Understand the hardware/software interface


Course Prerequisite(s)

CS 120A / EE 120A


Textbook and Reading Material

The textbook and reading material are optional, and may be helpful supplement to the material covered in the lectures and assignments.
- Patterson & Hennessy, Computer Organization and Design: The Hardware/Software Interface, 5th Edition
- Reading material will be available on Canvas


Discussion Forum

We will be using Piazza as our class forum, and our primary way of communication outside of class. All general inquiries must be made on Piazza. For group-specific questions or private questions, you can either email me or post a private question on Piazza.

Grading and Policies

Grading Breakdown (Total 103%)

- Homework assignments: 29% (HW0: 1%, HW2-Hw9: each 4%, one homeworks with lowest score will be dropped)
- Exams (throughout the course): 56% (Exam1-Exam8: each 8%, one exams with lowest score will be dropped)
- Lab Assignemnts: 14% (Lab1-Lab2: each 7%)
- In-class activities: 4%



Class Policies

Late submission: We do not accept any late submission for the exams. HWs have 5% hourly penalty for late submission (up to 10 hours). You are allowed to skip one of the assignments and one of the mini exams with no penalty. Use these freebies prudently. If you choose to submit all the assignments or all the exams, the lowest score of the assignments and exams will be dropped.

Cheating policy: Working with others on assignments is a good way to learn the material and is encouraged. However, there are limits to the degree of cooperation that is permitted. Students may discuss among themselves the meaning of homework problems and possible approaches to solving them. Any written portion of an assignment, however, is to be done strictly on an individual basis. You may not copy from another student or from any other source, and you may not allow another student to copy your work. Exams should be done individually and no collaboration in any form with others are permitted. Any violation of the above is considered to be cheating and will result in a failing grade in the class (no exceptions).

Errors in grading: If you feel there has been an error in how an assignment or test was graded, you have one week from when the assignment is returned to bring it to our attention. You must submit (via email to the instructor AND the graders) a written description of the problem. Neither I nor the graders will discuss regrades without receiving an email from you about it first.

Solutions: The solutions to the homework assignments and exams will be discussed in the discussion sessions.

Grades: Your score will be available on Canvas.



Grading Scale

A+: 97 and above
A: 94-96.9
A-: 90-93.9
B+: 87-89.9
B: 84-86.9
B-: 80-83.9
C+: 77-79.9
C: 74-76.9
C-: 70-73.9
D+: 67-69.9
D: 64-66.9
D-: 60-63.9
F: Below 60



Academic Integrity

Here at UCR we are committed to upholding and promoting the values of the Tartan Soul: Integrity, Accountability, Excellence, and Respect. As a student in this class, it is your responsibility to act in accordance with these values by completing all assignments in the manner described, and by informing the instructor of suspected acts of academic misconduct by your peers. By doing so, you will not only affirm your own integrity, but also the integrity of the intellectual work of this University, and the degree which it represents. Should you choose to commit academic misconduct in this class, you will be held accountable according to the policies set forth by the University, and will incur appropriate consequences both in this class and from Student Conduct and Academic Integrity Programs. For more information regarding University policy and its enforcement, please visit: http://conduct.ucr.edu.



Student Resources

◆ If you need special accomodation, please either contact me or find more information here: "UCR campus resources"

Course Schedule

- The following schedule is tentative and is subject to change.
- Course content are posted in Canvas.

NOTE : Exact date and time for HW release, HW due, and Exam should be check on Canvas (this schedule only show the week each HW or exam is released/due, not the exact day of the week)

.


Week Topic Reading Assignment Release Assignment Due Exam Lab
1 Introduction & Fundamental Concepts Ch 1 HW0 Release (Self Introduction)
2 Instruction Set Architecture 1 Ch 2 HW1 Release (ISA1) HW0 Due
3 Instruction Set Architecture 2 Ch 2 HW2 Release (ISA2) HW1 Due
4 Arithmetic & Logic Ch 3 & Ch 4.1-4.2 HW3 Release (Arithmetic/Logic) HW2 Due Exam1 (ISA1)
5 Processor Control and Datapath Ch 4.3-4.4 HW4 Release (Control/Datapath) HW3 Due Exam2 (ISA2) Lab (Part1&2) Release
6 Processor Pipelining Ch 4.5-4.6 HW5 Release (Pipelinig) HW4 Due Exam3 (Arithmetic/Logic)
7 Pipeline Hazards Ch 4.7-4.9 HW6 Release (Pipeline Hazards) HW5 Due Exam4 (Control/Datapath)
8 Caches Ch 5.3-5.4 HW7 Release (Caches) HW6 Due Exam5 (Pipelining)
9 Virtual Memory Ch 5.7 HW8 Release (Virtual Memory HW7 Due Exam6 (Pipeline Hazards) Lab Due
10 Virtual Memory and Review Ch 5.7 HW8 Due Exam7 (Caches)
11 Exam8 (Virtual Memory)