EE 248: Computer-Aided Logic Synthesis for Digital Systems

← 2010-11 2011-12 2012-13 →
← 2010-11 changes (lax) changes (strict) ▾ 2012-13 → 2012-13 →

Units: 4

Hours: Lecture, 3 hours; discussion, 1 hour

Catalog page 258

Prerequisites: CS 120A/EE 120A

Description: Introduces funda- mental theory and techniques for design and analysis of digital circuits. Provides detailed understanding of basic logic synthesis and analysis algorithms. Presents combinational circuit optimization (two-level and mul- tilevel synthesis), sequential circuit optimization (state encoding and retiming), timing analysis, testing, logic verification, and low paper design techniques.

Credit: May be taken Satisfactory (S) or No Credit (NC) with consent of instructor and graduate advisor.

Derived Information — The following is not part of the official catalog but is computed from catalog data.
Prerequisite graph not available.
Enrollment History (from UCR Banner, not catalog)
Combined: CS 248 / EE 248
Year F W S Su Total
2022-23 18/54 18/54
2021-22 19/54 19/54