Wei Wu

Ph.D. Candidate

Department of Computer Science and Engineering

University of California, Riverside

Email: wwu@cs.ucr.edu

I am a Ph.D. candidate in Department of Computer Science and Engineering at University of California, Riverside. My advisor is Dr. Jun Yang, and co-advisor is Dr. Sheldon Tan. 

Research Interest

 

Low power and thermal aware microprocessor design

Low power cache, register design

Network processor design and verification

 

Education

Jan 2004 ~ Till Date   Computer Science Dept., University of California, Riverside,  

Sep 2002 ~ Dec 2003  ECECS Dept., University of Cincinnati, Cincinnati,          

Sep 1996 ~ Jul 2000    Radio Engineering Dept., Southeast University, Nanjing, China      B.S.

 

Work Experience

 

Jun 2007 ~ Sep 2007   Intel Corporation, CTG/MTL/OML, Hillsboro, Oregon

Jun 2006 ~ Dec 2006   Intel Corporation, CTG/MTL/MRL, Hillsboro, Oregon

Jun 2000 ~ Jun 2002   Inst. of RF & OE ICs, Nanjing, China

 

Publication

Conference Paper

ICCD'07 Wei Wu, Jun Yang, Sheldon Tan, Shih-Lien Lu, "Improving the reliability of On-chip Data Caches Under Process Variations", International Conference on Computer Design, October, 2007. (Best Paper Award)
DAC'06 Wei Wu, Lingling Jin, Jun Yang, Pu Liu, Sheldon Tan, "An Efficient method For Functional Unit Power Estimation in Modern Microprocessors", Design Automation Conference, July, 2006.
ICCD'06 Lingling Jin, Wei Wu, Jun Yang, Chuanjun Zhang, Youtao Zhang, "Reduce Register File Leakage Through Cell Discharging", October, 2006.
ICESS'05 L Jin, W Wu, J Yang, C Zhang, Y Zhang, "Dynamic Co-allocation of Resources for Level One Caches", International Conference on Embedded Software and Systems, Xi'an, China, Dec.,2005
ICCD'05 H. Li, P. Liu, Z. Qi, L. Jin, W. Wu, S. X.-D. Tan, and J. Yang, "Efficient thermal simulation for run-time temperature tracking and management",  pp.130-133, San Jose, CA 2005
ICCAD'05 P. Liu, Z. Qi, H. Li, L. Jin, W. Wu, S. X.-D. Tan and J. Yang, "Fast thermal simulation for architecture level dynamic thermal management",  pp.639-644, San Jose, CA, Nov. 2005.
DATE '05 J. Yu, W. Wu, X. Chen, H. Hsieh, J. Yang, and F. Balarin. "Assertion-Based Design Exploration of DVS in Network Processor Architectures", Munich, Germany, March, 2005.  
HLDVT '04 J. Yu, W. Wu, X. Chen, H. Hsieh, J. Yang, and F. Balarin, "Assertion-Based Power/Performance Analysis of Network Processor Architectures", in Proceedings of International Workshop on High Level Design Validation and Test, Sonoma Valley, CA, November 2004.  

Journal Paper

ACM TODAES Wei Wu, Lingling Jin, Jun Yang, Pu Liu, Sheldon X.-D. Tan, "Efficient Power and Temperature Sensing in OS for Microprocessors at Runtime", Special issue on Demonstrable Software System and Hardware Platforms, ACM Transactions on Design Automation of Electronic Systems. 
IEEE TCAD P. Liu, H. Li, L. Jin, W. Wu, S. X.-D. Tan and J. Yang, "Thermal simulation for run-time temperature tracking and management", Transactions on Computer-Aided Design of Integrated Circuits and Systems
  W. Zhao; Z. Wang; W. Wu, et al. 1.25Gbps Serializer CMOS IC, in Journal of Research & Progress of Solid State Electronics, vol.23, no 1, Feb 2003. p.73-78  
  W. Zhao; Z. Wang; W. Wu, et al. Gigabit-Ethernet Synchronization Detector Integrated Circuit, in Journal of Southeast University, vol.32, no.2 March 2002. p. 161-5.