Vijayanand "Vijay" Nagarajan

Vijayanand "Vijay" Nagarajan

Computer Science Ph.D. Student
Department of Computer Science and Engineering
University of California, Riverside
Engineering BU2, Room 463
Riverside, CA 92521

Office Phone: (+1) 951-827-2001
E-mail: vijay [at] cs [dot] ucr [dot] edu

Biography
Research Interests
Education
Research Experience
Teaching Experience
Publications
Patents
Professional Activities
Personal

Biography

I graduated with a PhD from The Department of Computer Science and Engineering at the University of California, Riverside in September 2009, under the direction of Prof. Rajiv Gupta.

I will be joining the School of Informatics at The University of Edinburgh as a Lecturer (Assistant Professor) in October 2009.

Research Interests

Compiler Optimizations, Architecture Support, Software/Hardware collaborative Techniques for enhancing security, reliability and performance of multicores.

Education

PhD in Computer Science, UCR, September 2009.
M.S in Computer Science, University of Arizona, May 2005.
B.E (Bachelor of Engineering) in Computer Science, University of Madras, March 2003.

Research Experience

Research Assistant - University of California, Riverside, August 2007-present.
- Support for efficient monitoring in multicores [ISCA 2009] [SIGOPS] [VEE 2009] [PADTAD 2008].
- Speculative Parallelization for multicores [MICRO 2008] [IJPP]
Research Intern - Programming Systems Lab, Intel, May 2006-August 2006.
- Efficient information flow tracking using multicores [INTERACT 2008] [ICSM 2007a].
Research Assistant - University of Arizona, May 2004 - August 2007.
- Secure processors [HiPEAC 2007] [Trans. HiPEAC]
- Dynamic matching of program versions [ICSM 2007b]

Teaching Experience

Teaching Assistant - Advanced Computer Architecture - Winter 2009, UCR.
- Helped in designing the project, graded the projects and answered students' queries.
Grader - Compiler Construction - Winter 2008, UCR.
- Helped in designing the project, graded the projects and answered students' queries.
Guest Lectures - Principles of Compilation - Spring 2007, Arizona.
- Lead the discussion for two lectures in this compiler course.

Publications

Journal

[TOPLAS]	D.Jeffrey, V. Nagarajan, R.Gupta and N.Gupta Execution Supression: An Automated Iterative Technique for locating Memory Errors, ACM Transactions on Programming Languages and Systems, accepted October 2009.
[SIGOPS]	V. Nagarajan and R.Gupta, Runtime Monitoring on Multicores via OASES, ACM SIGOPS Operating Systems Review, special issue on the interaction among the OS, Compilers, and Multicore Processors, 10 pages, to appear April 2009 (Invited Paper).
[Trans. HiPEAC]	V.Nagarajan, R. Gupta, and A.Krishnaswamy, Compiler-Assisted Memory Encryption for Embedded Processors Transactions on High Performance Embedded Architectures and Compilers, Vol. 2, No. 1, pages 23-44, Springer Verlag, 2009 (Invited Paper -- special issue of selected papers from HiPEAC Conference).
[IJPP]	C. Tian, M.Feng, V. Nagarajan and R. Gupta, Speculative Parallelization of Sequential Loops On Multicores, International Journal of Parallel Programming,, accepted May 2009.
[SP&E]	C. Tian, V. Nagarajan, R. Gupta, and S. Tallam, Automated Dynamic Detection of Busy-wait Synchronizations, Software - Practice and Experience, accepted Feb 2009.

Conference

[ISCA 2009]	V. Nagarajan and R.Gupta, ECMon: Exposing Cache Events for Monitoring, ACM/IEEE 36th International Symposium on Computer Architecture, Austin, Texas, to appear June 2009.
[ISMM 2009]	V. Nagarajan, D. Jeffrey and R. Gupta, Self Recovery in Server Programs, International Symposium on Memory Management, Dublin, Ireland, to appear June 2009.
[VEE 2009]	V. Nagarajan and R.Gupta, Architectural Support for Shadow Memory in Multiprocessors, ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 10 pages, Washington DC, March 2009.
[MICRO 2008]	C. Tian, M. Feng, V. Nagarajan, and R. Gupta, Copy or Discard Execution Model For Speculative Parallelization On Multicores, IEEE/ACM 41st International Symposium on Microarchitecture, pages 330-341, Lake Como, Italy, Nov. 2008.
[ISSTA 2008]	C. Tian, V. Nagarajan, R. Gupta, and S. Tallam, Dynamic Recognition of Synchronization Operations for Improved Data Race Detection, SIGSOFT International Symposium on Software Testing and Analysis, pages 143-154, Seattle, July 2008.
[ICSM 2007a]	V. Nagarajan, D. Jeffrey, R. Gupta, and N. Gupta, ONTRAC: A System for Efficient ONline TRACing for Debugging, International Conference on Software Maintenance, pages 445-454, Paris, September 2007.
[ICSM 2007b]	V. Nagarajan, R. Gupta, X. Zhang, M. Madou, B. De Sutter, and K. De Bosschere, Matching Control Flow of Program Versions, International Conference on Software Maintenance, pages 84-93, Paris, September 2007.
[HiPEAC 2007]	V.Nagarajan, R. Gupta, and A.Krishnaswamy, Compiler-Assisted Memory Encryption for Embedded Processors International Conference on High Performance Embedded Architectures and Compilers, Springer Verlag, LNCS 4367, pages 7-22, Ghent, Belgium, January 2007.

Workshop

[LCPC 2009]	V. Nagarajan and R.Gupta, Speculative Optimizations for Parallel Programs on Multicores, 22nd International Workshop on Languages and Compilers for Parallel Computing, Newark, Delaware, October 2009..
[PADTAD 2008]	V. Nagarajan and R.Gupta, Support for Symmetric Shadow Memory in Multiprocessors, Workshop on Parallel and Distributed Systems: Testing, Analysis, and Debugging, (colocated with ISSTA), 9 pages, Seattle, July 2008.
[NSFNGS 2008]	R. Gupta, N. Gupta, X. Zhang, D. Jeffrey, V. Nagarajan, S. Tallam and C. Tian Scalable Dynamic Information Flow Tracking and its Applications, NSF Next Generation Software Workshop, colocated with IPDPS, pages 1-5, Florida, April 2008.
[STMCS 2008]	C. Tian, V. Nagarajan, and R. Gupta, Synchronization Aware Conflict Resolution for Runtime Monitoring Using Transactional Memory, Workshop on Software Tools for Multicore Systems, (colocated with CGO), 6 pages, Boston, April 2008.
[INTERACT 2008]	V. Nagarajan, H-S.Kim, Y.Wu and R. Gupta, Dynamic Information Flow Tracking on Multicores, Workshop on Interaction between Compilers and Computer Architectures, (colocated with HPCA), 10 pages, Salt Lake City, Feb. 2008.

US Patent Pending

Software Flow Tracking using Multiple threads.
Inventors: V. Nagarajan, H-S. Kim (Intel), Y. Wu (Intel), and R. Gupta.

Professional Activities

Reviewed papers for ASPLOS, PLDI, POPL, HPCA, ISCA, MICRO, CASES, HiPEAC, CGO, LCTES, TACO and TECS.
Member of IEEE and ACM

Personal

Citizenship: Indian.
VISA Status F1.
Music: I play the violin and the electric guitar and am part of SRUTI, a music band based in Tucson, Arizona. Waves, Saraswati, Folk and Sud are some of our compositions.
Cricket: I am a left handed opening batsman and played for the Wildcats team in the Arizona Cricket league. Currently I play for the Cougars team in the Southern California Cricket Association.