-- Copyright 2000 UCR all rights reserved
-- this program may be copy or altered so
-- long as this header stays intake
-- Original design Randy January rjanuary@cs.ucr.edu

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;

entity SCPU_TB is
end SCPU_TB;

architecture beh of SCPU_TB is

component scpu_master 
    port (
	 clk            : in std_logic;
	 reset          : in std_logic;
	 scpu_out       : out unsigned (31 downto 0)
        );    
end component;

--*****************************************************************************

signal reset  : std_logic := '1';
signal clk    : std_logic := '0';
signal tb_out : unsigned (31 downto 0);

--*****************************************************************************

begin  

    reset <= '0' after 50 ns;
    clk   <= not clk after 25 ns;

    scpu : scpu_master port map(clk, reset, tb_out);   

     process
       begin
         wait for 83000 ns;
         assert (tb_out = 4) report "Error!" severity error;
       end process;
      
end beh;

configuration CFG_SCPU_TB of SCPU_TB is
    for beh
    end for;
end CFG_SCPU_TB;