-- Copyright 2000 UCR all rights reserved
-- this program may be copy or altered so
-- long as this header stays intake
-- Original design Randy January rjanuary@cs.ucr.edu

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;

entity scpu_shftr is
  
  port (
    reset    : in  std_logic;
    shft_sel : in unsigned (1 downto 0); 
    Input    : in  unsigned (31 downto 0);
    Output   : out unsigned (31 downto 0)
    );

end scpu_shftr;

architecture beh of scpu_shftr is

begin  

  process(reset, shft_sel, Input)
    begin

--****************************************************************************
      
      if (reset = '1') then
        
        Output <= "00000000000000000000000000000000";

--****************************************************************************
        
      else
        
        case shft_sel is

          -- pass
          when "00" => Output <= Input;

          -- shift right
          when "01" => 
		  Output(0) <= Input(1);
		  Output(1) <= Input(2);
		  Output(2) <= Input(3);
		  Output(3) <= Input(4);
		  Output(4) <= Input(5);
		  Output(5) <= Input(6);	
		  Output(6) <= Input(7);
		  Output(7) <= Input(8);
                  Output(8) <= Input(9);
		  Output(9) <= Input(10);
		  Output(10) <= Input(11);
		  Output(11) <= Input(12);
		  Output(12) <= Input(13);
		  Output(13) <= Input(14);	
		  Output(14) <= Input(15);
		  Output(15) <= Input(16);
                  Output(16) <= Input(17);
		  Output(17) <= Input(18);
		  Output(18) <= Input(19);
		  Output(19) <= Input(20);
		  Output(20) <= Input(21);
		  Output(21) <= Input(22);	
		  Output(22) <= Input(23);
		  Output(23) <= Input(24);
                  Output(24) <= Input(25);
		  Output(25) <= Input(26);
		  Output(26) <= Input(27);
		  Output(27) <= Input(28);
		  Output(28) <= Input(29);
		  Output(29) <= Input(30);	
		  Output(30) <= Input(31);
		  Output(31) <= '0';

          -- shift left
          when "10" =>
                  Output(31) <= Input(30);
		  Output(30) <= Input(29);
		  Output(29) <= Input(28);
		  Output(28) <= Input(27);
		  Output(27) <= Input(26);
		  Output(26) <= Input(25);	
		  Output(25) <= Input(24);
		  Output(24) <= Input(23);
                  Output(23) <= Input(22);
		  Output(22) <= Input(21);
		  Output(21) <= Input(20);
		  Output(20) <= Input(19);
		  Output(19) <= Input(18);
		  Output(18) <= Input(17);	
		  Output(17) <= Input(16);
		  Output(16) <= Input(15);
                  Output(15) <= Input(14);
		  Output(14) <= Input(13);
		  Output(13) <= Input(12);
		  Output(12) <= Input(11);
		  Output(11) <= Input(10);
		  Output(10) <= Input(9);	
		  Output(9) <= Input(8);
		  Output(8) <= Input(7);
		  Output(7) <= Input(6);
		  Output(6) <= Input(5);
		  Output(5) <= Input(4);
		  Output(4) <= Input(3);
		  Output(3) <= Input(2);
		  Output(2) <= Input(1);	
		  Output(1) <= Input(0);
		  Output(0) <= '0';
          when others => null;
        end case;
      end if;
    end process;
end beh;