-- Copyright 2000 UCR all rights reserved
-- this program may be copy or altered so
-- long as this header stays intake
-- Original design Randy January rjanuary@cs.ucr.edu

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use WORK.SCPU_LIB.all;

entity scpu_rom is
	port (
		rst     : in std_logic;
		clk     : in std_logic;
		address : in integer;
		command : out unsigned (31 downto 0)
		);
end scpu_rom;
architecture beh of scpu_rom is
--************************************************
type ROM is array (0 to 20) of unsigned (31 downto 0);
constant program : ROM := (
"00000000000000000000000000100011",
"00000000000001000000000000000000",
"00000000000010000000000000000001",
"00000000000011000000000000000000",
"00000000000100000000000000000001",
"01001000000000000000000000001000",
"00000000000000000000000000000000",
"01001000000000000000010000010011",
"00010000000000000000000000000100",
"01001000000000000000000000001100",
"00011000000011000000011000000010",
"01001000000000000000100000010011",
"00001000000011000000010000000001",
"00000000000001000000000000000000",
"00011000000001000000001000000010",
"00000000000010000000000000000000",
"00011000000010000000010000000011",
"00010000000000000000000000000100",
"01001000000000000000000000001100",
"00011000000000000000000000000011",
"11111000000000000000000000000000"
);
--********************************************************

begin
	process(rst, clk, address)
		begin
			if (rst = '1') then
				command <= CD_32;
		elsif (clk'event and clk = '1') then
				command <= program(address);
			end if;
		end process;
end beh;