-- Copyright 2000 UCR all rights reserved
-- this program may be copy or altered so
-- long as this header stays intake
-- Original design Randy January rjanuary@cs.ucr.edu

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
use WORK.scpu_lib.all;

entity scpu_reg is
  port (
    clk        : in std_logic;
    reset      : in std_logic;
    wrt_sel    : in std_logic;
    rd_sel1    : in std_logic;
    rd_sel2    : in std_logic;
    W_address  : in unsigned (8 downto 0);
    R_address1 : in unsigned (8 downto 0);
    R_address2 : in unsigned (8 downto 0);
    Input      : in  unsigned (31 downto 0);
    Output1    : out unsigned (31 downto 0);
    Output2    : out unsigned (31 downto 0)
    );
end scpu_reg;

architecture beh of scpu_reg is

type Rfile is array (0 to 32) of unsigned(31 downto 0);
signal reg : Rfile;

begin
  
  process(clk, reset, wrt_sel, rd_sel1, rd_sel2, W_address, R_address1,
          R_address2, Input)
    begin
      
--***************************************************************************

      if (reset = '1') then
        for i in 0 to 32 loop
          reg(i) <= CZ_32;
        end loop;
      
        Output1 <= CZ_32;
        Output2 <= CZ_32;

--***************************************************************************
        
    elsif (clk'event and clk = '1') then

      if (wrt_sel = '1') then
         reg(conv_integer(W_address)) <= Input;
      end if;

      if (rd_sel1 = '1') then
        Output1 <= reg(conv_integer(R_address1));
      else
        Output1 <= CZ_32;
      end if;
      
      if (rd_sel2 = '1')  then
        Output2 <= reg(conv_integer(R_address2));
      else
        Output2 <= CZ_32;  
      end if;

    end if;
  end process;      
end beh;