-- Copyright 2000 UCR all rights reserved
-- this program may be copy or altered so
-- long as this header stays intake
-- Original design Randy January rjanuary@cs.ucr.edu

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use WORK.SCPU_LIB.all;

entity scpu_master is
   port (
	 clk            : in std_logic;
	 reset          : in std_logic;
	 scpu_out       : out unsigned (31 downto 0)
        );    
end scpu_master;

architecture str of scpu_master is

component scpu_cntrl
    port(
	clk         : in std_logic;
	reset       : in std_logic;
        jmp         : in std_logic;
        rom_command : in unsigned (31 downto 0);
        interrupt   : in std_logic;
        W_sel       : out std_logic;
        R1_sel      : out std_logic;
        R2_sel      : out std_logic;
        O_sel       : out std_logic;
        r_wEn       : out std_logic;
        Zcheck      : out std_logic;
        signChk     : out std_logic;
        sign_out    : in std_logic;
        mux_sel     : out unsigned (1 downto 0);
        sh_sel      : out unsigned (1 downto 0);
        alu_sel     : out unsigned (2 downto 0);
        rom_address : out integer;
        ram_address : out unsigned (8 downto 0);
        imm         : out unsigned (31 downto 0);
        Wrf_address : out unsigned (8 downto 0);
        Rrf1_address : out unsigned (8 downto 0);
        Rrf2_address : out unsigned (8 downto 0)
	);	
end component;

--*****************************************************************************

component scpu_rom 
  port (
    rst     : in  std_logic;
    clk     : in  std_logic;
    address : in  integer;
    command : out unsigned (31 downto 0)
    );
end component;

component scpu_ram 
  port (
    clk        : in std_logic;
    reset      : in std_logic;
    data_in    : in unsigned (31 downto 0);
    address    : in unsigned (8 downto 0);
  --  cs         : in std_logic;
    r_wEn      : in std_logic;
    Output     : out unsigned (31 downto 0)
    );
end component;
  
component scpu_mux 
  port (
    reset   : in  std_logic;
    mux_sel : in  unsigned (1 downto 0);
    dp_in   : in  unsigned (31 downto 0);
    imm_in  : in  unsigned (31 downto 0);
    ram_in  : in  unsigned (31 downto 0);
    mux_out : out unsigned (31 downto 0)
    );
end component;

component scpu_reg
  port (
    clk        : in std_logic;
    reset      : in std_logic;
    wrt_sel    : in std_logic;
    rd_sel1    : in std_logic;
    rd_sel2    : in std_logic;
    W_address  : in unsigned (8 downto 0);
    R_address1 : in unsigned (8 downto 0);
    R_address2 : in unsigned (8 downto 0);
    Input      : in unsigned (31 downto 0);
    Output1    : out unsigned (31 downto 0);
    Output2    : out unsigned (31 downto 0)
    );
end component;

component scpu_alu 
  port (		  
    reset     : in std_logic;
    alu_sel   : in unsigned (2 downto 0);
    input1    : in unsigned (31 downto 0);
    input2    : in unsigned (31 downto 0);
    output    : out unsigned (31 downto 0);
    interrupt : out std_logic
    );
end component;

component scpu_shftr 
  
  port (
    reset    : in std_logic;
    shft_sel : in unsigned (1 downto 0); 
    Input    : in unsigned (31 downto 0);
    Output   : out unsigned (31 downto 0)
    );

end component;	

component scpu_obuff 
	port(
	reset  : in std_logic;
	O_sel  : in std_logic;
	Input  : in unsigned (31 downto 0);
	Output : out unsigned (31 downto 0)
	);
end component;

component scpu_sign 
  
  port (
    reset    : in  std_logic; 
    Input    : in  unsigned (31 downto 0);
    signChk  : in std_logic;
    sign_out   : out std_logic
    );

end component;


component scpu_zero 
  
  port (
    reset   : in std_logic;
    ck_en   : in std_logic;
    Input   : in unsigned (31 downto 0);
    Zero_ck : out std_logic
    );
  
end component;

--***************************************************************************

signal r_wEn, W_sel, R1_sel, R2_sel, O_sel, Zcheck : std_logic;
signal haltsig, z_out, int, sign, sign_out : std_logic;
signal mux_sel, sh_sel : unsigned (1 downto 0); 
signal alu_sel : unsigned (2 downto 0);
signal rom_address : integer;
signal ram_address : unsigned (8 downto 0);
signal Wrf_address, Rrf1_address, Rrf2_address : unsigned (8 downto 0);
signal ram_out, mux_out, reg_out1, reg_out2, alu_out, sh_out,
       obuf_out : unsigned (31 downto 0);
signal imm : unsigned (31 downto 0);
signal rom_command : unsigned (31 downto 0);

--***************************************************************************

begin
  
 
  ROM   : scpu_rom port map(reset, clk, rom_address, rom_command);

  RAM   : scpu_ram port map(clk, reset, sh_out, ram_address, r_wEn, ram_out);
  
  CNTRL : scpu_cntrl port map(clk, reset, z_out, rom_command, int, W_sel,
                              R1_sel, R2_sel, O_sel, r_wEn, Zcheck, sign,
                              sign_out, mux_sel, sh_sel, alu_sel, rom_address,
                              ram_address, imm, Wrf_address, Rrf1_address,
                              Rrf2_address);

  MUX   : scpu_mux port map( reset,  mux_sel, sh_out, imm, ram_out, mux_out);

  REG   : scpu_reg port map( clk, reset, W_sel, R1_sel, R2_sel, Wrf_address,
                            Rrf1_address, Rrf2_address, mux_out, reg_out1,
			    reg_out2);

  ALU   : scpu_alu port map( reset, alu_sel, reg_out1, reg_out2, alu_out, int);

  SHFT  : scpu_shftr port map(reset, sh_sel, alu_out, sh_out);

  CSIGN : scpu_sign port map(reset, sh_out, sign, sign_out);

  CK_Z  : scpu_zero port map(reset,  Zcheck, sh_out, z_out);
  
  OBUF  : scpu_obuff port map( reset, O_sel, sh_out, obuf_out);

  process(clk, reset, obuf_out)
    begin
      scpu_out <= obuf_out;
  end process;
end str;