-- Copyright 2000 UCR all rights reserved
-- this program may be copy or altered so
-- long as this header stays intake
-- Original design Randy January rjanuary@cs.ucr.edu

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use Work.scpu_lib.all;

entity scpu_zero is
  
  port (
    reset   : in std_logic;
    ck_en   : in std_logic;
    Input   : in unsigned (31 downto 0);
    Zero_ck : out std_logic
    );
  
end scpu_zero;

architecture beh of scpu_zero is

signal mask : unsigned (31 downto 0);

begin

  process (reset, ck_en, Input)
  begin
    
    if (reset = '1') then
      Zero_ck <= '0';

    elsif (ck_en = '1') then
      
      if (Input = CZ_32) then
        Zero_ck <= '0';
      else
        Zero_ck <= '1';
      end if;
    else
      Zero_ck <= '0';
    end if;
    
  end process;  

end beh;


