-- Copyright 2000 UCR all rights reserved
-- this program may be copy or altered so
-- long as this header stays intake
-- Original design Randy January rjanuary@cs.ucr.edu

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
use WORK.scpu_lib.all;

entity scpu_ram is
  port (
    clk        : in std_logic;
    reset      : in std_logic;
    data_in    : in unsigned (31 downto 0);
    address    : in unsigned (8 downto 0);
  --  cs         : in std_logic;
    r_wEn      : in std_logic;
    Output     : out unsigned (31 downto 0)
    );
end scpu_ram;

architecture beh of scpu_ram is

type RAM_TYPE is array (0 to 32) of unsigned(31 downto 0);
signal ram : RAM_TYPE;

begin  -- beh
  process(clk, reset, data_in, address, r_wEn)
    begin
      
    if (reset = '1') then
      
      for i in 0 to 32 loop
        ram(i) <= CZ_32;
      end loop;
      
      Output <= CZ_32;
      
    elsif (clk'event and clk = '1') then 
      
      if (r_wEn = '1') then

        ram(conv_integer(address)) <= data_in;

      else 

        Output <= ram(conv_integer(address));

      end if;
    
    end if;
  end process;      
end beh;




