--Componet library for the LC-2 microcontroller
--Created by:
--Eric Frohnhoefer
--Ron Feliciano

--16 bit adder-----------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity adder is
   port(A : in std_logic_vector (15 downto 0);
      B : in std_logic_vector (15 downto 0);
      O : out std_logic_vector (15 downto 0));
end adder;

architecture bhv of adder is
begin
process(A,B)
begin

   O <= A+B;
	
end process;
end bhv;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

--LC-2 ALU---------------------------------------
entity LC2_ALU is
   port( A: in std_logic_vector (15 downto 0); 
      B: in std_logic_vector (15 downto 0);
      S: in std_logic_vector (1 downto 0);
      O: out std_logic_vector (15 downto 0));
end LC2_ALU;

architecture bhv of LC2_ALU is
begin
   process(A, B, S)
begin
	
   case S is 
      when "00" => O <= A+B;
      when "01" => O <= A and B;
      when "10" => O <= A;
      when "11" => O <= not A;
      when others => null;
   end case;
	
end process;
end bhv;

--concatenate [8:0] of IR with [15:9] of PC------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity cat is
   port(A : in std_logic_vector (8 downto 0);
      B : in std_logic_vector (6 downto 0);
      O : out std_logic_vector (15 downto 0));
end cat;

architecture bhv of cat is
begin
process(A,B)
begin

   O <= B & A;
	
end process;
end bhv;

--incrementor------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity increment is
   port(data: in std_logic_vector (15 downto 0); 
      O: out std_logic_vector (15 downto 0));
end increment;

architecture bhv of increment is
begin
process(data)
begin

   O <= data + 1;

end process;
end bhv;

--4 to 1 mux-------------------------------------
library IEEE; 
use IEEE.STD_LOGIC_1164.ALL;

entity mux4 is
   port(c : in std_logic_vector(15 downto 0);
      d : in std_logic_vector(15 downto 0);
      e : in std_logic_vector(15 downto 0);
      f : in std_logic_vector(15 downto 0);
      s : in std_logic_vector(1 downto 0);
      muxoutput	: out std_logic_vector(15 downto 0));
end mux4;


architecture bhv of mux4 is
begin
   process(s,c,d,e,f)
begin
   case s is
      when "00"=> muxoutput <= c;
      when "01"=> muxoutput <= d;
      when "10"=> muxoutput <= e;
      when "11" => muxoutput <= f;
      when others => null;
   end case;
   end process;
end bhv;

--2 to 1 mux-------------------------------------
library IEEE; 
use IEEE.STD_LOGIC_1164.ALL;

entity mux2 is
   port(a: in std_logic_vector(15 downto 0); 
      b: in std_logic_vector(15 downto 0);
      s: in std_logic;
      mux2output : out std_logic_vector(15 downto 0));
end mux2;


architecture bhv of mux2 is
begin
   process(s,a,b)
begin
   if (s = '1') then
      mux2output <= a;
   elsif (s = '0') then
      mux2output <= b;  
   end if;
   end process;
end bhv;

--logic used to set NZP bits---------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity NZP_logic is
   port(data: in std_logic_vector (15 downto 0); 
      O: out std_logic_vector (2 downto 0));
end NZP_logic;

architecture bhv of NZP_logic is
begin
   process(data)
begin
if (data(15) = '1') then
   O <= "100";
elsif (data > "0000000000000000") then
   O <= "001";
elsif (data = "0000000000000000") then
   O <= "010";
end if;

end process;
end bhv;

--16 bit register--------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity reg is
   port(clk : in std_logic; 
      load : in std_logic;
      data : in std_logic_vector (15 downto 0); 
      O : out std_logic_vector (15 downto 0);
      clear : in std_logic);
end reg;

architecture bhv of reg is
begin
process(clk,load)
   variable temp:std_logic_vector (15 downto 0);
begin
   if (clear='1') then
      temp:="0000000000000000";
   else
      if (clk'event and clk='1') then
      if load='1' then
        O<=data;
            temp:=data;
      else
         O<=temp;
      end if;
   end if;
   end if;
end process;
end bhv;


--8x16 register bank-----------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity register_file is
   port(clk : in std_logic;
      DR_enable : in std_logic;
      DR_address : in std_logic_vector (2 downto 0);
			  
      SR1_address: in std_logic_vector(2 downto 0);
      SR2_address: in std_logic_vector(2 downto 0);	  
			  
      data_in: in std_logic_vector (15 downto 0);
      SR1_out: out std_logic_vector (15 downto 0);
      SR2_out: out std_logic_vector (15 downto 0));						   
end register_file;

architecture bhv of register_file is

   type memory is array (0 to 7) of std_logic_vector(15 downto 0);
   signal reg: memory;

begin	
   read:process(clk,SR1_address,SR2_address)
begin 
   if(clk'event and clk='1') then
      SR1_out <= reg(conv_integer(SR1_address));
      SR2_out <= reg(conv_integer(SR2_address));
   end if;
end process	;

write:process(clk, DR_enable, DR_address, data_in)
begin
   if(clk'event and clk='1') then
      if(DR_enable = '1') then
         reg(conv_integer(DR_address))<=data_in;
      end if;
   end if;
end process;
end bhv; 

--NZP Register-----------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity NZP_reg is
   port(clk : in std_logic; 
      load : in std_logic;
      data : in std_logic_vector (2 downto 0); 
      O : out std_logic_vector (2 downto 0);
      clear : in std_logic);
end NZP_reg;

architecture bhv of NZP_reg is
begin
process(clk,load)
   variable temp:std_logic_vector (2 downto 0);
begin
   if (clear='1') then
      temp:="000";
   else
      if (clk'event and clk='1') then
      if load='1' then
         O<=data;
         temp:=data;
      else
         O<=temp;
   end if;
end if;
end if;
end process;
end bhv;

--sign extend the last 5 bits of the IR----------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity sext is
   port(A : in std_logic_vector (4 downto 0);
      O : out std_logic_vector (15 downto 0));
end sext;

architecture bhv of sext is
begin
process(A)
begin
   if (A(4) = '1') then
      O <= "11111111111" & A;
   elsif (A(4) = '0') then
      O <= "00000000000" & A;
   end if;	
end process;
end bhv;

--tri-state buffer-------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity tri_state is
   port(data_in: in STD_LOGIC_VECTOR (15 downto 0);
      s: in STD_LOGIC;
      data_out: out STD_LOGIC_VECTOR (15 downto 0));
end tri_state;

architecture bhv of tri_state is
begin
   process(data_in, s)
begin
   if (s='1') then
      data_out <= data_in;
   elsif (s='0') then
      data_out <= "ZZZZZZZZZZZZZZZZ";
   end if;
end process;
end bhv;

--zero extend bits [5:0] of the IR---------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity zext10 is
   port(A : in std_logic_vector (5 downto 0);
      O : out std_logic_vector (15 downto 0));
end zext10;

architecture bhv of zext10 is
begin
process(A)
begin

   O <= "0000000000" & A;
	
end process;
end bhv;

--zero extend bits [7:0] of the IR---------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity zext8 is
   port(A : in std_logic_vector (7 downto 0);
      O : out std_logic_vector (15 downto 0));
end zext8;

architecture bhv of zext8 is
begin
process(A)
begin

   O <= "00000000" & A;
	
end process;
end bhv;

--additional memory logic------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity mem_logic is
   port(read_write :in std_logic;
      MAR         :in std_logic_vector (15 downto 0);
      MIO_enable  :in std_logic;
	  mem_enable  :out std_logic;
	  mux_sel_out :out std_logic_vector(1 downto 0);
	  KBSR_ld     :out std_logic;
	  CRTDR_ld    :out std_logic;
	  CRTSR_ld    :out std_logic);
end mem_logic;

architecture bhv of mem_logic is
begin
   process(MAR, MIO_enable, read_write)
begin
   case MAR is
      when "1111001111111100" =>
         if (MIO_enable = '1' and read_write = '1') then
            mem_enable <= '0';
            mux_sel_out <= "10";
            KBSR_ld <= '0';
            CRTSR_ld <= '0';
            CRTDR_ld <= '0';
		 elsif (MIO_enable = '1' and read_write = '0')then
            mem_enable <= '0';
            KBSR_ld <= '0';
            CRTSR_ld <= '1';
            CRTDR_ld <= '0';
         else
            mem_enable <= '0';
            KBSR_ld <= '0';
            CRTSR_ld <= '0';
            CRTDR_ld <= '0';
	     end if;
      when "1111001111111111" =>
         if (MIO_enable = '1' and read_write = '0') then
            mem_enable <= '0';
            KBSR_ld <= '0';
            CRTSR_ld <= '0';
            CRTDR_ld <= '1';         
         else
            mem_enable <= '0';
            KBSR_ld <= '0';
            CRTSR_ld <= '0';
            CRTDR_ld <= '0';  
         end if;
      when "1111010000000000" =>
         if(MIO_enable = '1' and read_write = '1') then
            mem_enable <= '0';
            mux_sel_out <= "01";
            KBSR_ld <= '0';
            CRTSR_ld <= '0';
            CRTDR_ld <= '0';
         elsif (MIO_enable = '1' and read_write = '0') then
            mem_enable <= '0';
            KBSR_ld <= '1';
            CRTSR_ld <= '0';
            CRTDR_ld <= '0';
         else
            mem_enable <= '0';
            KBSR_ld <= '0';
            CRTSR_ld <= '0';
            CRTDR_ld <= '0';
         end if;
	  when "1111010000000001" =>
         if(MIO_enable = '1' and read_write = '1') then
            mem_enable <= '0';
            mux_sel_out <= "00";
            KBSR_ld <= '0';
            CRTSR_ld <= '0';
            CRTDR_ld <= '0';
         else
            mem_enable <= '0';
            KBSR_ld <= '0';
            CRTSR_ld <= '0';
            CRTDR_ld <= '0';
         end if;
      when others =>
         if (MIO_enable = '1' and read_write = '1') then
            mem_enable <= '1';
            mux_sel_out <= "11";
            KBSR_ld <= '0';
            CRTSR_ld <= '0';
            CRTDR_ld <= '0';
         elsif (MIO_enable = '1' and read_write = '0') then
            mem_enable <= '1';
            KBSR_ld <= '0';
            CRTSR_ld <= '0';
            CRTDR_ld <= '0';
         else
            mem_enable <= '0';
            KBSR_ld <= '0';
            CRTSR_ld <= '0';
            CRTDR_ld <= '0';
         end if;
   end case;
end process;
end bhv;