library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; package CONV_PACK_LC2_all is -- define attributes attribute ENUM_ENCODING : STRING; end CONV_PACK_LC2_all; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity register_file is port( clk, DR_enable : in std_logic; DR_address, SR1_address, SR2_address : in std_logic_vector (0 to 2); data_in : in std_logic_vector (0 to 15) ; SR1_out, SR2_out : out std_logic_vector (0 to 15)); end register_file; architecture SYN of register_file is component FD1 port( D, CP : in std_logic; Q, QN : out std_logic); end component; component FDS2L port( D, CP, CR, LD : in std_logic; Q, QN : out std_logic); end component; component ND4 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component IV port( A : in std_logic; Z : out std_logic); end component; component AN3 port( A, B, C : in std_logic; Z : out std_logic); end component; component NR3 port( A, B, C : in std_logic; Z : out std_logic); end component; component AO2 port( A, B, C, D : in std_logic; Z : out std_logic); end component; signal member46_12_port, larray355_7_1_port, larray355_1_15_port, larray355_7_11_port, larray355_3_3_port, larray_1_5_port, larray_5_7_port , larray355_2_9_port, member185_13_port, larray_5_12_port, larray355_2_0_port, larray355_0_13_port, member46_2_port, larray_4_4_port , larray355_6_2_port, larray355_7_8_port, larray_2_10_port, larray_0_6_port, larray_4_14_port, larray_5_3_port, larray_3_12_port, larray_1_1_port, larray355_3_7_port, larray_4_9_port, larray355_7_15_port , larray355_1_11_port, larray355_7_5_port, larray_0_2_port, larray_2_14_port, larray_4_10_port, larray_4_0_port, member46_6_port, larray355_6_6_port, larray355_6_13_port, larray_1_8_port, larray355_2_4_port, larray_5_8_port, larray355_6_4_port, larray355_0_15_port, larray355_6_11_port, member46_4_port, member185_15_port, larray355_2_6_port, larray_0_0_port, larray_4_12_port, larray_4_2_port, member46_14_port, larray_0_9_port, larray355_3_5_port, larray355_1_13_port, larray_5_1_port, larray355_7_7_port, larray_3_10_port, larray_1_3_port, larray_5_14_port, larray_4_6_port, member46_0_port, member185_11_port, larray_2_12_port, larray355_3_8_port, larray_0_4_port, larray355_2_2_port, larray355_0_11_port, larray355_6_15_port, member46_10_port, member46_9_port, larray_1_7_port, larray355_6_0_port, larray355_6_9_port, larray_5_10_port, larray_5_5_port , larray_3_14_port, larray355_7_3_port, larray355_7_13_port, larray355_3_1_port, larray355_5_5_port, larray_6_9_port, larray355_4_12_port, member185_6_port, larray355_1_7_port, larray_6_11_port, larray_0_15_port, larray_3_1_port, larray_7_3_port, larray_3_8_port, larray355_0_4_port, larray355_3_10_port, larray355_5_14_port, larray355_4_6_port, larray_1_13_port, larray_6_0_port, larray_2_2_port, larray_7_7_port, larray_6_15_port, larray355_0_9_port, larray_0_11_port, larray_3_5_port, larray355_1_3_port , larray355_2_12_port, larray355_5_1_port, larray_2_6_port, member185_2_port, larray355_5_8_port, larray_7_13_port, larray_6_4_port, larray355_4_2_port, larray355_5_10_port, larray355_3_14_port, larray355_0_0_port, larray355_4_0_port, member185_0_port, larray355_5_12_port, larray355_0_2_port, larray_2_4_port, larray355_1_8_port, larray_1_15_port, larray_6_6_port, larray_7_11_port, larray355_1_1_port, larray355_2_10_port, larray355_4_14_port, larray355_5_3_port, member185_9_port, larray_7_5_port, larray355_4_9_port , larray_0_13_port, larray_3_7_port, larray_1_11_port, larray_7_15_port, larray_6_2_port, larray_2_0_port, member185_4_port, larray355_0_6_port, larray_7_8_port, larray355_3_12_port, larray_6_13_port, larray355_4_4_port, larray_3_3_port, larray_7_1_port, larray355_5_7_port, larray_2_9_port, larray355_2_14_port, larray355_4_10_port, larray355_1_5_port, larray_6_3_port, larray_7_14_port, larray_1_10_port, larray_2_1_port, member185_5_port, larray355_3_13_port, larray355_0_7_port, larray355_4_5_port, larray_7_9_port, larray_6_12_port , larray_3_2_port, larray_7_0_port, larray355_4_11_port, larray355_2_15_port, larray355_5_6_port, larray355_1_4_port, member185_1_port, larray_2_8_port, larray355_4_1_port, larray355_0_3_port , larray355_5_13_port, larray355_1_9_port, larray_2_5_port, larray_7_10_port, larray_1_14_port, larray_6_7_port, larray355_1_0_port, larray355_5_2_port, member185_8_port, larray355_2_11_port, larray355_4_15_port, larray355_4_8_port, larray_7_4_port, larray_0_12_port, larray_3_6_port, larray_0_10_port, larray_7_6_port, larray_6_14_port, larray_3_4_port, larray355_0_8_port, larray355_1_2_port , larray355_5_0_port, larray355_2_13_port, larray_2_7_port, larray_6_5_port, larray_7_12_port, larray355_5_9_port, larray355_4_3_port , larray355_0_1_port, larray355_3_15_port, member185_3_port, larray355_5_11_port, larray_6_8_port, larray355_4_13_port, larray355_5_4_port, larray355_1_6_port, member185_7_port, larray_0_14_port, larray_6_10_port, larray_3_0_port, larray_7_2_port, larray_3_9_port, larray355_3_11_port, larray355_5_15_port, larray355_0_5_port, larray355_4_7_port, larray_1_12_port, larray_6_1_port , larray_2_3_port, member185_10_port, larray_4_7_port, larray_0_5_port, larray_2_13_port, larray355_3_9_port, larray355_2_3_port, member46_11_port, member46_8_port, member46_1_port, larray355_6_1_port, larray355_0_10_port, larray355_6_14_port, larray_1_6_port, larray_5_4_port, larray_3_15_port, larray_5_11_port, larray355_6_8_port, larray355_7_2_port, member46_5_port, larray355_3_0_port, larray355_7_12_port, larray_5_9_port, larray355_0_14_port, larray355_6_10_port, larray355_6_5_port, larray355_2_7_port, member185_14_port, larray_4_13_port, larray_0_1_port, larray_4_3_port, member46_15_port, larray_0_8_port, larray355_1_12_port, larray355_3_4_port, larray355_7_6_port, larray_5_0_port, larray_5_15_port , larray_3_11_port, larray_1_2_port, larray_5_2_port, larray_3_13_port, larray_1_0_port, larray355_1_10_port, larray355_7_14_port, larray_4_11_port, larray_0_3_port, larray_4_8_port, larray355_3_6_port, larray355_7_4_port, larray_2_15_port, larray_4_1_port, larray355_6_12_port, member46_7_port, member46_13_port, larray355_6_7_port, larray355_2_5_port, larray_1_9_port, larray355_7_0_port, larray355_3_2_port, larray355_7_10_port, larray355_1_14_port, larray355_2_8_port, larray_1_4_port, larray_5_6_port , larray_5_13_port, member185_12_port, larray355_2_1_port, member46_3_port, larray355_6_3_port, larray355_0_12_port, larray_4_5_port , larray355_7_9_port, larray_4_15_port, larray_0_7_port, larray_2_11_port , n602, n603, n604, n605, n606, n607, n608, n609, n610, n611, n612, n613, n614, n615, n616, n617, n618, n619, n620, n621, n622, n623, n624, n625, n626, n627, n628, n629, n630, n631, n632, n633, n634, n635, n636, n637, n638, n639, n640, n641, n642, n643, n644, n645, n646, n647, n648, n649, n650, n651, n652, n653, n654, n655, n656, n657, n658, n659, n660, n661, n662, n663, n664, n665, n666, n667, n668, n669, n670, n671, n672, n673, n674, n675, n676, n677, n678, n679, n680, n681, n682, n683, n684, n685, n686, n687, n688, n689, n690, n691, n692, n693, n694, n695, n696, n697, n698, n699, n700, n701, n702, n703, n704, n705, n706, n707, n708, n709, n710, n711, n712, n713, n714, n715, n716, n717, n718, n719, n720, n721, n722, n723, n724, n725, n726, n727, n728, n729, n730, n731, n732, n733, n734, n735, n736, n737, n738, n739, n740, n741, n742, n743, n744, n745, n746, n747, n748, n749, n750, n751, n752, n753, n754, n755, n756, n757, n758, n759, n760, n761, n762, n763, n764, n765, n766, n767, n768, n769, n770, n771, n772, n773, n774, n775, n776, n777, n778, n779, n780, n781, n782, n783, n784, n785, n786, n787, n788, n789, n790, n791, n792, n793, n794, n795, n796, n797, n798, n799, n800, n801, n802, n803, n804, n805, n806, n807, n808, n809, n810, n811, n812, n813, n814, n815, n816, n817, n818, n819, n820, n821, n822, n823, n824, n825, n826, n827, n828, n829, n830, n831, n832, n833, n834, n835, n836, n837, n838, n839, n840, n841, n842, n843, n844, n845, n846, n847, n848, n849, n850, n851, n852, n853, n854, n855, n856, n857, n858, n859, n860, n861, n862, n863, n864, n865, n866, n867, n868, n869, n870, n871, n872, n873, n874, n875, n876, n877, n878, n879, n880, n881, n882, n883, n884, n885, n886, n887, n888, n889, n890, n891, n892, n893, n894, n895, n896, n897, n898, n899, n900, n901, n902, n903, n904, n905, n906, n907, n908, n909, n910, n911, n912, n913, n914, n915, n916, n917, n918, n919, n920, n921, n922, n923, n924, n925, n926, n927, n928, n929, n930, n931, n932, n933, n934, n935, n936, n937, n938, n939, n940, n941, n942, n943, n944, n945, n946, n947, n948, n949, n950, n951, n952, n953, n954, n955, n956, n957, n958, n959, n960, n961, n962, n963, n964, n965, n966, n967, n968, n969, n970, n971, n972, n973, n974, n975, n976, n977, n978, n979, n980, n981, n982, n983, n984, n985, n986, n987, n988, n989, n990, n991, n992, n993, n994, n995, n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008 , n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023 : std_logic; begin SR1_out_reg_15_label : FD1 port map( D => member46_15_port, CP => clk, Q => SR1_out(0), QN => open); SR1_out_reg_14_label : FD1 port map( D => member46_14_port, CP => clk, Q => SR1_out(1), QN => open); SR1_out_reg_13_label : FD1 port map( D => member46_13_port, CP => clk, Q => SR1_out(2), QN => open); SR1_out_reg_12_label : FD1 port map( D => member46_12_port, CP => clk, Q => SR1_out(3), QN => open); SR1_out_reg_11_label : FD1 port map( D => member46_11_port, CP => clk, Q => SR1_out(4), QN => open); SR1_out_reg_10_label : FD1 port map( D => member46_10_port, CP => clk, Q => SR1_out(5), QN => open); SR1_out_reg_9_label : FD1 port map( D => member46_9_port, CP => clk, Q => SR1_out(6), QN => open); SR1_out_reg_8_label : FD1 port map( D => member46_8_port, CP => clk, Q => SR1_out(7), QN => open); SR1_out_reg_7_label : FD1 port map( D => member46_7_port, CP => clk, Q => SR1_out(8), QN => open); SR1_out_reg_6_label : FD1 port map( D => member46_6_port, CP => clk, Q => SR1_out(9), QN => open); SR1_out_reg_5_label : FD1 port map( D => member46_5_port, CP => clk, Q => SR1_out(10), QN => open); SR1_out_reg_4_label : FD1 port map( D => member46_4_port, CP => clk, Q => SR1_out(11), QN => open); SR1_out_reg_3_label : FD1 port map( D => member46_3_port, CP => clk, Q => SR1_out(12), QN => open); SR1_out_reg_2_label : FD1 port map( D => member46_2_port, CP => clk, Q => SR1_out(13), QN => open); SR1_out_reg_1_label : FD1 port map( D => member46_1_port, CP => clk, Q => SR1_out(14), QN => open); SR1_out_reg_0_label : FD1 port map( D => member46_0_port, CP => clk, Q => SR1_out(15), QN => open); SR2_out_reg_15_label : FD1 port map( D => member185_15_port, CP => clk, Q => SR2_out(0), QN => open); SR2_out_reg_14_label : FD1 port map( D => member185_14_port, CP => clk, Q => SR2_out(1), QN => open); SR2_out_reg_13_label : FD1 port map( D => member185_13_port, CP => clk, Q => SR2_out(2), QN => open); SR2_out_reg_12_label : FD1 port map( D => member185_12_port, CP => clk, Q => SR2_out(3), QN => open); SR2_out_reg_11_label : FD1 port map( D => member185_11_port, CP => clk, Q => SR2_out(4), QN => open); SR2_out_reg_10_label : FD1 port map( D => member185_10_port, CP => clk, Q => SR2_out(5), QN => open); SR2_out_reg_9_label : FD1 port map( D => member185_9_port, CP => clk, Q => SR2_out(6), QN => open); SR2_out_reg_8_label : FD1 port map( D => member185_8_port, CP => clk, Q => SR2_out(7), QN => open); SR2_out_reg_7_label : FD1 port map( D => member185_7_port, CP => clk, Q => SR2_out(8), QN => open); SR2_out_reg_6_label : FD1 port map( D => member185_6_port, CP => clk, Q => SR2_out(9), QN => open); SR2_out_reg_5_label : FD1 port map( D => member185_5_port, CP => clk, Q => SR2_out(10), QN => open); SR2_out_reg_4_label : FD1 port map( D => member185_4_port, CP => clk, Q => SR2_out(11), QN => open); SR2_out_reg_3_label : FD1 port map( D => member185_3_port, CP => clk, Q => SR2_out(12), QN => open); SR2_out_reg_2_label : FD1 port map( D => member185_2_port, CP => clk, Q => SR2_out(13), QN => open); SR2_out_reg_1_label : FD1 port map( D => member185_1_port, CP => clk, Q => SR2_out(14), QN => open); SR2_out_reg_0_label : FD1 port map( D => member185_0_port, CP => clk, Q => SR2_out(15), QN => open); reg_reg_7_0_label : FDS2L port map( D => larray355_7_0_port, CP => clk, CR => n896, LD => DR_enable, Q => larray_7_0_port, QN => open); reg_reg_7_1_label : FDS2L port map( D => larray355_7_1_port, CP => clk, CR => n897, LD => DR_enable, Q => larray_7_1_port, QN => open); reg_reg_7_2_label : FDS2L port map( D => larray355_7_2_port, CP => clk, CR => n898, LD => DR_enable, Q => larray_7_2_port, QN => open); reg_reg_7_3_label : FDS2L port map( D => larray355_7_3_port, CP => clk, CR => n899, LD => DR_enable, Q => larray_7_3_port, QN => open); reg_reg_7_4_label : FDS2L port map( D => larray355_7_4_port, CP => clk, CR => n900, LD => DR_enable, Q => larray_7_4_port, QN => open); reg_reg_7_5_label : FDS2L port map( D => larray355_7_5_port, CP => clk, CR => n901, LD => DR_enable, Q => larray_7_5_port, QN => open); reg_reg_7_6_label : FDS2L port map( D => larray355_7_6_port, CP => clk, CR => n902, LD => DR_enable, Q => larray_7_6_port, QN => open); reg_reg_7_7_label : FDS2L port map( D => larray355_7_7_port, CP => clk, CR => n903, LD => DR_enable, Q => larray_7_7_port, QN => open); reg_reg_7_8_label : FDS2L port map( D => larray355_7_8_port, CP => clk, CR => n904, LD => DR_enable, Q => larray_7_8_port, QN => open); reg_reg_7_9_label : FDS2L port map( D => larray355_7_9_port, CP => clk, CR => n905, LD => DR_enable, Q => larray_7_9_port, QN => open); reg_reg_7_10_label : FDS2L port map( D => larray355_7_10_port, CP => clk, CR => n906, LD => DR_enable, Q => larray_7_10_port, QN => open); reg_reg_7_11_label : FDS2L port map( D => larray355_7_11_port, CP => clk, CR => n907, LD => DR_enable, Q => larray_7_11_port, QN => open); reg_reg_7_12_label : FDS2L port map( D => larray355_7_12_port, CP => clk, CR => n908, LD => DR_enable, Q => larray_7_12_port, QN => open); reg_reg_7_13_label : FDS2L port map( D => larray355_7_13_port, CP => clk, CR => n909, LD => DR_enable, Q => larray_7_13_port, QN => open); reg_reg_7_14_label : FDS2L port map( D => larray355_7_14_port, CP => clk, CR => n910, LD => DR_enable, Q => larray_7_14_port, QN => open); reg_reg_7_15_label : FDS2L port map( D => larray355_7_15_port, CP => clk, CR => n911, LD => DR_enable, Q => larray_7_15_port, QN => open); reg_reg_6_0_label : FDS2L port map( D => larray355_6_0_port, CP => clk, CR => n912, LD => DR_enable, Q => larray_6_0_port, QN => open); reg_reg_6_1_label : FDS2L port map( D => larray355_6_1_port, CP => clk, CR => n913, LD => DR_enable, Q => larray_6_1_port, QN => open); reg_reg_6_2_label : FDS2L port map( D => larray355_6_2_port, CP => clk, CR => n914, LD => DR_enable, Q => larray_6_2_port, QN => open); reg_reg_6_3_label : FDS2L port map( D => larray355_6_3_port, CP => clk, CR => n915, LD => DR_enable, Q => larray_6_3_port, QN => open); reg_reg_6_4_label : FDS2L port map( D => larray355_6_4_port, CP => clk, CR => n916, LD => DR_enable, Q => larray_6_4_port, QN => open); reg_reg_6_5_label : FDS2L port map( D => larray355_6_5_port, CP => clk, CR => n917, LD => DR_enable, Q => larray_6_5_port, QN => open); reg_reg_6_6_label : FDS2L port map( D => larray355_6_6_port, CP => clk, CR => n918, LD => DR_enable, Q => larray_6_6_port, QN => open); reg_reg_6_7_label : FDS2L port map( D => larray355_6_7_port, CP => clk, CR => n919, LD => DR_enable, Q => larray_6_7_port, QN => open); reg_reg_6_8_label : FDS2L port map( D => larray355_6_8_port, CP => clk, CR => n920, LD => DR_enable, Q => larray_6_8_port, QN => open); reg_reg_6_9_label : FDS2L port map( D => larray355_6_9_port, CP => clk, CR => n921, LD => DR_enable, Q => larray_6_9_port, QN => open); reg_reg_6_10_label : FDS2L port map( D => larray355_6_10_port, CP => clk, CR => n922, LD => DR_enable, Q => larray_6_10_port, QN => open); reg_reg_6_11_label : FDS2L port map( D => larray355_6_11_port, CP => clk, CR => n923, LD => DR_enable, Q => larray_6_11_port, QN => open); reg_reg_6_12_label : FDS2L port map( D => larray355_6_12_port, CP => clk, CR => n924, LD => DR_enable, Q => larray_6_12_port, QN => open); reg_reg_6_13_label : FDS2L port map( D => larray355_6_13_port, CP => clk, CR => n925, LD => DR_enable, Q => larray_6_13_port, QN => open); reg_reg_6_14_label : FDS2L port map( D => larray355_6_14_port, CP => clk, CR => n926, LD => DR_enable, Q => larray_6_14_port, QN => open); reg_reg_6_15_label : FDS2L port map( D => larray355_6_15_port, CP => clk, CR => n927, LD => DR_enable, Q => larray_6_15_port, QN => open); reg_reg_5_0_label : FDS2L port map( D => larray355_5_0_port, CP => clk, CR => n928, LD => DR_enable, Q => larray_5_0_port, QN => open); reg_reg_5_1_label : FDS2L port map( D => larray355_5_1_port, CP => clk, CR => n929, LD => DR_enable, Q => larray_5_1_port, QN => open); reg_reg_5_2_label : FDS2L port map( D => larray355_5_2_port, CP => clk, CR => n930, LD => DR_enable, Q => larray_5_2_port, QN => open); reg_reg_5_3_label : FDS2L port map( D => larray355_5_3_port, CP => clk, CR => n931, LD => DR_enable, Q => larray_5_3_port, QN => open); reg_reg_5_4_label : FDS2L port map( D => larray355_5_4_port, CP => clk, CR => n932, LD => DR_enable, Q => larray_5_4_port, QN => open); reg_reg_5_5_label : FDS2L port map( D => larray355_5_5_port, CP => clk, CR => n933, LD => DR_enable, Q => larray_5_5_port, QN => open); reg_reg_5_6_label : FDS2L port map( D => larray355_5_6_port, CP => clk, CR => n934, LD => DR_enable, Q => larray_5_6_port, QN => open); reg_reg_5_7_label : FDS2L port map( D => larray355_5_7_port, CP => clk, CR => n935, LD => DR_enable, Q => larray_5_7_port, QN => open); reg_reg_5_8_label : FDS2L port map( D => larray355_5_8_port, CP => clk, CR => n936, LD => DR_enable, Q => larray_5_8_port, QN => open); reg_reg_5_9_label : FDS2L port map( D => larray355_5_9_port, CP => clk, CR => n937, LD => DR_enable, Q => larray_5_9_port, QN => open); reg_reg_5_10_label : FDS2L port map( D => larray355_5_10_port, CP => clk, CR => n938, LD => DR_enable, Q => larray_5_10_port, QN => open); reg_reg_5_11_label : FDS2L port map( D => larray355_5_11_port, CP => clk, CR => n939, LD => DR_enable, Q => larray_5_11_port, QN => open); reg_reg_5_12_label : FDS2L port map( D => larray355_5_12_port, CP => clk, CR => n940, LD => DR_enable, Q => larray_5_12_port, QN => open); reg_reg_5_13_label : FDS2L port map( D => larray355_5_13_port, CP => clk, CR => n941, LD => DR_enable, Q => larray_5_13_port, QN => open); reg_reg_5_14_label : FDS2L port map( D => larray355_5_14_port, CP => clk, CR => n942, LD => DR_enable, Q => larray_5_14_port, QN => open); reg_reg_5_15_label : FDS2L port map( D => larray355_5_15_port, CP => clk, CR => n943, LD => DR_enable, Q => larray_5_15_port, QN => open); reg_reg_4_0_label : FDS2L port map( D => larray355_4_0_port, CP => clk, CR => n944, LD => DR_enable, Q => larray_4_0_port, QN => open); reg_reg_4_1_label : FDS2L port map( D => larray355_4_1_port, CP => clk, CR => n945, LD => DR_enable, Q => larray_4_1_port, QN => open); reg_reg_4_2_label : FDS2L port map( D => larray355_4_2_port, CP => clk, CR => n946, LD => DR_enable, Q => larray_4_2_port, QN => open); reg_reg_4_3_label : FDS2L port map( D => larray355_4_3_port, CP => clk, CR => n947, LD => DR_enable, Q => larray_4_3_port, QN => open); reg_reg_4_4_label : FDS2L port map( D => larray355_4_4_port, CP => clk, CR => n948, LD => DR_enable, Q => larray_4_4_port, QN => open); reg_reg_4_5_label : FDS2L port map( D => larray355_4_5_port, CP => clk, CR => n949, LD => DR_enable, Q => larray_4_5_port, QN => open); reg_reg_4_6_label : FDS2L port map( D => larray355_4_6_port, CP => clk, CR => n950, LD => DR_enable, Q => larray_4_6_port, QN => open); reg_reg_4_7_label : FDS2L port map( D => larray355_4_7_port, CP => clk, CR => n951, LD => DR_enable, Q => larray_4_7_port, QN => open); reg_reg_4_8_label : FDS2L port map( D => larray355_4_8_port, CP => clk, CR => n952, LD => DR_enable, Q => larray_4_8_port, QN => open); reg_reg_4_9_label : FDS2L port map( D => larray355_4_9_port, CP => clk, CR => n953, LD => DR_enable, Q => larray_4_9_port, QN => open); reg_reg_4_10_label : FDS2L port map( D => larray355_4_10_port, CP => clk, CR => n954, LD => DR_enable, Q => larray_4_10_port, QN => open); reg_reg_4_11_label : FDS2L port map( D => larray355_4_11_port, CP => clk, CR => n955, LD => DR_enable, Q => larray_4_11_port, QN => open); reg_reg_4_12_label : FDS2L port map( D => larray355_4_12_port, CP => clk, CR => n956, LD => DR_enable, Q => larray_4_12_port, QN => open); reg_reg_4_13_label : FDS2L port map( D => larray355_4_13_port, CP => clk, CR => n957, LD => DR_enable, Q => larray_4_13_port, QN => open); reg_reg_4_14_label : FDS2L port map( D => larray355_4_14_port, CP => clk, CR => n958, LD => DR_enable, Q => larray_4_14_port, QN => open); reg_reg_4_15_label : FDS2L port map( D => larray355_4_15_port, CP => clk, CR => n959, LD => DR_enable, Q => larray_4_15_port, QN => open); reg_reg_3_0_label : FDS2L port map( D => larray355_3_0_port, CP => clk, CR => n960, LD => DR_enable, Q => larray_3_0_port, QN => open); reg_reg_3_1_label : FDS2L port map( D => larray355_3_1_port, CP => clk, CR => n961, LD => DR_enable, Q => larray_3_1_port, QN => open); reg_reg_3_2_label : FDS2L port map( D => larray355_3_2_port, CP => clk, CR => n962, LD => DR_enable, Q => larray_3_2_port, QN => open); reg_reg_3_3_label : FDS2L port map( D => larray355_3_3_port, CP => clk, CR => n963, LD => DR_enable, Q => larray_3_3_port, QN => open); reg_reg_3_4_label : FDS2L port map( D => larray355_3_4_port, CP => clk, CR => n964, LD => DR_enable, Q => larray_3_4_port, QN => open); reg_reg_3_5_label : FDS2L port map( D => larray355_3_5_port, CP => clk, CR => n965, LD => DR_enable, Q => larray_3_5_port, QN => open); reg_reg_3_6_label : FDS2L port map( D => larray355_3_6_port, CP => clk, CR => n966, LD => DR_enable, Q => larray_3_6_port, QN => open); reg_reg_3_7_label : FDS2L port map( D => larray355_3_7_port, CP => clk, CR => n967, LD => DR_enable, Q => larray_3_7_port, QN => open); reg_reg_3_8_label : FDS2L port map( D => larray355_3_8_port, CP => clk, CR => n968, LD => DR_enable, Q => larray_3_8_port, QN => open); reg_reg_3_9_label : FDS2L port map( D => larray355_3_9_port, CP => clk, CR => n969, LD => DR_enable, Q => larray_3_9_port, QN => open); reg_reg_3_10_label : FDS2L port map( D => larray355_3_10_port, CP => clk, CR => n970, LD => DR_enable, Q => larray_3_10_port, QN => open); reg_reg_3_11_label : FDS2L port map( D => larray355_3_11_port, CP => clk, CR => n971, LD => DR_enable, Q => larray_3_11_port, QN => open); reg_reg_3_12_label : FDS2L port map( D => larray355_3_12_port, CP => clk, CR => n972, LD => DR_enable, Q => larray_3_12_port, QN => open); reg_reg_3_13_label : FDS2L port map( D => larray355_3_13_port, CP => clk, CR => n973, LD => DR_enable, Q => larray_3_13_port, QN => open); reg_reg_3_14_label : FDS2L port map( D => larray355_3_14_port, CP => clk, CR => n974, LD => DR_enable, Q => larray_3_14_port, QN => open); reg_reg_3_15_label : FDS2L port map( D => larray355_3_15_port, CP => clk, CR => n975, LD => DR_enable, Q => larray_3_15_port, QN => open); reg_reg_2_0_label : FDS2L port map( D => larray355_2_0_port, CP => clk, CR => n976, LD => DR_enable, Q => larray_2_0_port, QN => open); reg_reg_2_1_label : FDS2L port map( D => larray355_2_1_port, CP => clk, CR => n977, LD => DR_enable, Q => larray_2_1_port, QN => open); reg_reg_2_2_label : FDS2L port map( D => larray355_2_2_port, CP => clk, CR => n978, LD => DR_enable, Q => larray_2_2_port, QN => open); reg_reg_2_3_label : FDS2L port map( D => larray355_2_3_port, CP => clk, CR => n979, LD => DR_enable, Q => larray_2_3_port, QN => open); reg_reg_2_4_label : FDS2L port map( D => larray355_2_4_port, CP => clk, CR => n980, LD => DR_enable, Q => larray_2_4_port, QN => open); reg_reg_2_5_label : FDS2L port map( D => larray355_2_5_port, CP => clk, CR => n981, LD => DR_enable, Q => larray_2_5_port, QN => open); reg_reg_2_6_label : FDS2L port map( D => larray355_2_6_port, CP => clk, CR => n982, LD => DR_enable, Q => larray_2_6_port, QN => open); reg_reg_2_7_label : FDS2L port map( D => larray355_2_7_port, CP => clk, CR => n983, LD => DR_enable, Q => larray_2_7_port, QN => open); reg_reg_2_8_label : FDS2L port map( D => larray355_2_8_port, CP => clk, CR => n984, LD => DR_enable, Q => larray_2_8_port, QN => open); reg_reg_2_9_label : FDS2L port map( D => larray355_2_9_port, CP => clk, CR => n985, LD => DR_enable, Q => larray_2_9_port, QN => open); reg_reg_2_10_label : FDS2L port map( D => larray355_2_10_port, CP => clk, CR => n986, LD => DR_enable, Q => larray_2_10_port, QN => open); reg_reg_2_11_label : FDS2L port map( D => larray355_2_11_port, CP => clk, CR => n987, LD => DR_enable, Q => larray_2_11_port, QN => open); reg_reg_2_12_label : FDS2L port map( D => larray355_2_12_port, CP => clk, CR => n988, LD => DR_enable, Q => larray_2_12_port, QN => open); reg_reg_2_13_label : FDS2L port map( D => larray355_2_13_port, CP => clk, CR => n989, LD => DR_enable, Q => larray_2_13_port, QN => open); reg_reg_2_14_label : FDS2L port map( D => larray355_2_14_port, CP => clk, CR => n990, LD => DR_enable, Q => larray_2_14_port, QN => open); reg_reg_2_15_label : FDS2L port map( D => larray355_2_15_port, CP => clk, CR => n991, LD => DR_enable, Q => larray_2_15_port, QN => open); reg_reg_1_0_label : FDS2L port map( D => larray355_1_0_port, CP => clk, CR => n992, LD => DR_enable, Q => larray_1_0_port, QN => open); reg_reg_1_1_label : FDS2L port map( D => larray355_1_1_port, CP => clk, CR => n993, LD => DR_enable, Q => larray_1_1_port, QN => open); reg_reg_1_2_label : FDS2L port map( D => larray355_1_2_port, CP => clk, CR => n994, LD => DR_enable, Q => larray_1_2_port, QN => open); reg_reg_1_3_label : FDS2L port map( D => larray355_1_3_port, CP => clk, CR => n995, LD => DR_enable, Q => larray_1_3_port, QN => open); reg_reg_1_4_label : FDS2L port map( D => larray355_1_4_port, CP => clk, CR => n996, LD => DR_enable, Q => larray_1_4_port, QN => open); reg_reg_1_5_label : FDS2L port map( D => larray355_1_5_port, CP => clk, CR => n997, LD => DR_enable, Q => larray_1_5_port, QN => open); reg_reg_1_6_label : FDS2L port map( D => larray355_1_6_port, CP => clk, CR => n998, LD => DR_enable, Q => larray_1_6_port, QN => open); reg_reg_1_7_label : FDS2L port map( D => larray355_1_7_port, CP => clk, CR => n999, LD => DR_enable, Q => larray_1_7_port, QN => open); reg_reg_1_8_label : FDS2L port map( D => larray355_1_8_port, CP => clk, CR => n1000, LD => DR_enable, Q => larray_1_8_port, QN => open); reg_reg_1_9_label : FDS2L port map( D => larray355_1_9_port, CP => clk, CR => n1001, LD => DR_enable, Q => larray_1_9_port, QN => open); reg_reg_1_10_label : FDS2L port map( D => larray355_1_10_port, CP => clk, CR => n1002, LD => DR_enable, Q => larray_1_10_port, QN => open); reg_reg_1_11_label : FDS2L port map( D => larray355_1_11_port, CP => clk, CR => n1003, LD => DR_enable, Q => larray_1_11_port, QN => open); reg_reg_1_12_label : FDS2L port map( D => larray355_1_12_port, CP => clk, CR => n1004, LD => DR_enable, Q => larray_1_12_port, QN => open); reg_reg_1_13_label : FDS2L port map( D => larray355_1_13_port, CP => clk, CR => n1005, LD => DR_enable, Q => larray_1_13_port, QN => open); reg_reg_1_14_label : FDS2L port map( D => larray355_1_14_port, CP => clk, CR => n1006, LD => DR_enable, Q => larray_1_14_port, QN => open); reg_reg_1_15_label : FDS2L port map( D => larray355_1_15_port, CP => clk, CR => n1007, LD => DR_enable, Q => larray_1_15_port, QN => open); reg_reg_0_0_label : FDS2L port map( D => larray355_0_0_port, CP => clk, CR => n1008, LD => DR_enable, Q => larray_0_0_port, QN => open); reg_reg_0_1_label : FDS2L port map( D => larray355_0_1_port, CP => clk, CR => n1009, LD => DR_enable, Q => larray_0_1_port, QN => open); reg_reg_0_2_label : FDS2L port map( D => larray355_0_2_port, CP => clk, CR => n1010, LD => DR_enable, Q => larray_0_2_port, QN => open); reg_reg_0_3_label : FDS2L port map( D => larray355_0_3_port, CP => clk, CR => n1011, LD => DR_enable, Q => larray_0_3_port, QN => open); reg_reg_0_4_label : FDS2L port map( D => larray355_0_4_port, CP => clk, CR => n1012, LD => DR_enable, Q => larray_0_4_port, QN => open); reg_reg_0_5_label : FDS2L port map( D => larray355_0_5_port, CP => clk, CR => n1013, LD => DR_enable, Q => larray_0_5_port, QN => open); reg_reg_0_6_label : FDS2L port map( D => larray355_0_6_port, CP => clk, CR => n1014, LD => DR_enable, Q => larray_0_6_port, QN => open); reg_reg_0_7_label : FDS2L port map( D => larray355_0_7_port, CP => clk, CR => n1015, LD => DR_enable, Q => larray_0_7_port, QN => open); reg_reg_0_8_label : FDS2L port map( D => larray355_0_8_port, CP => clk, CR => n1016, LD => DR_enable, Q => larray_0_8_port, QN => open); reg_reg_0_9_label : FDS2L port map( D => larray355_0_9_port, CP => clk, CR => n1017, LD => DR_enable, Q => larray_0_9_port, QN => open); reg_reg_0_10_label : FDS2L port map( D => larray355_0_10_port, CP => clk, CR => n1018, LD => DR_enable, Q => larray_0_10_port, QN => open); reg_reg_0_11_label : FDS2L port map( D => larray355_0_11_port, CP => clk, CR => n1019, LD => DR_enable, Q => larray_0_11_port, QN => open); reg_reg_0_12_label : FDS2L port map( D => larray355_0_12_port, CP => clk, CR => n1020, LD => DR_enable, Q => larray_0_12_port, QN => open); reg_reg_0_13_label : FDS2L port map( D => larray355_0_13_port, CP => clk, CR => n1021, LD => DR_enable, Q => larray_0_13_port, QN => open); reg_reg_0_14_label : FDS2L port map( D => larray355_0_14_port, CP => clk, CR => n1022, LD => DR_enable, Q => larray_0_14_port, QN => open); reg_reg_0_15_label : FDS2L port map( D => larray355_0_15_port, CP => clk, CR => n1023, LD => DR_enable, Q => larray_0_15_port, QN => open); U54 : ND4 port map( A => n602, B => n603, C => n604, D => n605, Z => member46_15_port); U55 : ND4 port map( A => n606, B => n607, C => n608, D => n609, Z => member46_14_port); U56 : ND4 port map( A => n610, B => n611, C => n612, D => n613, Z => member46_13_port); U57 : ND4 port map( A => n614, B => n615, C => n616, D => n617, Z => member46_12_port); U58 : ND4 port map( A => n618, B => n619, C => n620, D => n621, Z => member46_11_port); U59 : ND4 port map( A => n622, B => n623, C => n624, D => n625, Z => member46_10_port); U60 : ND4 port map( A => n626, B => n627, C => n628, D => n629, Z => member46_9_port); U61 : ND4 port map( A => n630, B => n631, C => n632, D => n633, Z => member46_8_port); U62 : ND4 port map( A => n634, B => n635, C => n636, D => n637, Z => member46_7_port); U63 : ND4 port map( A => n638, B => n639, C => n640, D => n641, Z => member46_6_port); U64 : ND4 port map( A => n642, B => n643, C => n644, D => n645, Z => member46_5_port); U65 : ND4 port map( A => n646, B => n647, C => n648, D => n649, Z => member46_4_port); U66 : ND4 port map( A => n650, B => n651, C => n652, D => n653, Z => member46_3_port); U67 : ND4 port map( A => n654, B => n655, C => n656, D => n657, Z => member46_2_port); U68 : ND4 port map( A => n658, B => n659, C => n660, D => n661, Z => member46_1_port); U69 : ND4 port map( A => n662, B => n663, C => n664, D => n665, Z => member46_0_port); U70 : ND4 port map( A => n666, B => n667, C => n668, D => n669, Z => member185_15_port); U71 : ND4 port map( A => n670, B => n671, C => n672, D => n673, Z => member185_14_port); U72 : ND4 port map( A => n674, B => n675, C => n676, D => n677, Z => member185_13_port); U73 : ND4 port map( A => n678, B => n679, C => n680, D => n681, Z => member185_12_port); U74 : ND4 port map( A => n682, B => n683, C => n684, D => n685, Z => member185_11_port); U75 : ND4 port map( A => n686, B => n687, C => n688, D => n689, Z => member185_10_port); U76 : ND4 port map( A => n690, B => n691, C => n692, D => n693, Z => member185_9_port); U77 : ND4 port map( A => n694, B => n695, C => n696, D => n697, Z => member185_8_port); U78 : ND4 port map( A => n698, B => n699, C => n700, D => n701, Z => member185_7_port); U79 : ND4 port map( A => n702, B => n703, C => n704, D => n705, Z => member185_6_port); U80 : ND4 port map( A => n706, B => n707, C => n708, D => n709, Z => member185_5_port); U81 : ND4 port map( A => n710, B => n711, C => n712, D => n713, Z => member185_4_port); U82 : ND4 port map( A => n714, B => n715, C => n716, D => n717, Z => member185_3_port); U83 : ND4 port map( A => n718, B => n719, C => n720, D => n721, Z => member185_2_port); U84 : ND4 port map( A => n722, B => n723, C => n724, D => n725, Z => member185_1_port); U85 : ND4 port map( A => n726, B => n727, C => n728, D => n729, Z => member185_0_port); U86 : IV port map( A => SR1_address(1), Z => n730); U87 : IV port map( A => SR1_address(2), Z => n731); U88 : AN3 port map( A => SR1_address(2), B => SR1_address(1), C => SR1_address(0), Z => n732); U89 : AN3 port map( A => SR1_address(1), B => n731, C => SR1_address(0), Z => n733); U90 : AN3 port map( A => SR1_address(2), B => n730, C => SR1_address(0), Z => n734); U91 : AN3 port map( A => n730, B => n731, C => SR1_address(0), Z => n735); U92 : NR3 port map( A => n730, B => SR1_address(0), C => n731, Z => n736); U93 : NR3 port map( A => SR1_address(2), B => SR1_address(0), C => n730, Z => n737); U94 : NR3 port map( A => SR1_address(1), B => SR1_address(0), C => n731, Z => n738); U95 : NR3 port map( A => SR1_address(0), B => SR1_address(2), C => SR1_address(1), Z => n739); U96 : IV port map( A => SR2_address(2), Z => n740); U97 : IV port map( A => SR2_address(1), Z => n741); U98 : AN3 port map( A => SR2_address(0), B => SR2_address(2), C => SR2_address(1), Z => n742); U99 : AN3 port map( A => SR2_address(0), B => n740, C => SR2_address(1), Z => n743); U100 : AN3 port map( A => SR2_address(2), B => n741, C => SR2_address(0), Z => n744); U101 : AN3 port map( A => n740, B => n741, C => SR2_address(0), Z => n745); U102 : NR3 port map( A => n740, B => SR2_address(0), C => n741, Z => n746); U103 : NR3 port map( A => SR2_address(2), B => SR2_address(0), C => n741, Z => n747); U104 : NR3 port map( A => SR2_address(0), B => SR2_address(1), C => n740, Z => n748); U105 : NR3 port map( A => SR2_address(1), B => SR2_address(0), C => SR2_address(2), Z => n749); U106 : IV port map( A => DR_address(1), Z => n750); U107 : IV port map( A => DR_address(2), Z => n751); U108 : AO2 port map( A => larray_7_9_port, B => n753, C => data_in(6), D => n754, Z => n752); U109 : AO2 port map( A => larray_7_8_port, B => n753, C => data_in(7), D => n754, Z => n755); U110 : AO2 port map( A => larray_7_7_port, B => n753, C => data_in(8), D => n754, Z => n756); U111 : AO2 port map( A => larray_7_6_port, B => n753, C => data_in(9), D => n754, Z => n757); U112 : AO2 port map( A => larray_7_5_port, B => n753, C => data_in(10), D => n754, Z => n758); U113 : AO2 port map( A => larray_7_4_port, B => n753, C => data_in(11), D => n754, Z => n759); U114 : AO2 port map( A => larray_7_3_port, B => n753, C => data_in(12), D => n754, Z => n760); U115 : AO2 port map( A => larray_7_2_port, B => n753, C => data_in(13), D => n754, Z => n761); U116 : AO2 port map( A => larray_7_1_port, B => n753, C => data_in(14), D => n754, Z => n762); U117 : AO2 port map( A => larray_7_15_port, B => n753, C => data_in(0), D => n754, Z => n763); U118 : AO2 port map( A => larray_7_14_port, B => n753, C => data_in(1), D => n754, Z => n764); U119 : AO2 port map( A => larray_7_13_port, B => n753, C => data_in(2), D => n754, Z => n765); U120 : AO2 port map( A => larray_7_12_port, B => n753, C => data_in(3), D => n754, Z => n766); U121 : AO2 port map( A => larray_7_11_port, B => n753, C => data_in(4), D => n754, Z => n767); U122 : AO2 port map( A => larray_7_10_port, B => n753, C => data_in(5), D => n754, Z => n768); U123 : AO2 port map( A => larray_7_0_port, B => n753, C => data_in(15), D => n754, Z => n769); U124 : AO2 port map( A => larray_6_9_port, B => n771, C => data_in(6), D => n772, Z => n770); U125 : AO2 port map( A => larray_6_8_port, B => n771, C => data_in(7), D => n772, Z => n773); U126 : AO2 port map( A => larray_6_7_port, B => n771, C => data_in(8), D => n772, Z => n774); U127 : AO2 port map( A => larray_6_6_port, B => n771, C => data_in(9), D => n772, Z => n775); U128 : AO2 port map( A => larray_6_5_port, B => n771, C => data_in(10), D => n772, Z => n776); U129 : AO2 port map( A => larray_6_4_port, B => n771, C => data_in(11), D => n772, Z => n777); U130 : AO2 port map( A => larray_6_3_port, B => n771, C => data_in(12), D => n772, Z => n778); U131 : AO2 port map( A => larray_6_2_port, B => n771, C => data_in(13), D => n772, Z => n779); U132 : AO2 port map( A => larray_6_1_port, B => n771, C => data_in(14), D => n772, Z => n780); U133 : AO2 port map( A => larray_6_15_port, B => n771, C => data_in(0), D => n772, Z => n781); U134 : AO2 port map( A => larray_6_14_port, B => n771, C => data_in(1), D => n772, Z => n782); U135 : AO2 port map( A => larray_6_13_port, B => n771, C => data_in(2), D => n772, Z => n783); U136 : AO2 port map( A => larray_6_12_port, B => n771, C => data_in(3), D => n772, Z => n784); U137 : AO2 port map( A => larray_6_11_port, B => n771, C => data_in(4), D => n772, Z => n785); U138 : AO2 port map( A => larray_6_10_port, B => n771, C => data_in(5), D => n772, Z => n786); U139 : AO2 port map( A => larray_6_0_port, B => n771, C => data_in(15), D => n772, Z => n787); U140 : AO2 port map( A => larray_5_9_port, B => n789, C => data_in(6), D => n790, Z => n788); U141 : AO2 port map( A => larray_5_8_port, B => n789, C => data_in(7), D => n790, Z => n791); U142 : AO2 port map( A => larray_5_7_port, B => n789, C => data_in(8), D => n790, Z => n792); U143 : AO2 port map( A => larray_5_6_port, B => n789, C => data_in(9), D => n790, Z => n793); U144 : AO2 port map( A => larray_5_5_port, B => n789, C => data_in(10), D => n790, Z => n794); U145 : AO2 port map( A => larray_5_4_port, B => n789, C => data_in(11), D => n790, Z => n795); U146 : AO2 port map( A => larray_5_3_port, B => n789, C => data_in(12), D => n790, Z => n796); U147 : AO2 port map( A => larray_5_2_port, B => n789, C => data_in(13), D => n790, Z => n797); U148 : AO2 port map( A => larray_5_1_port, B => n789, C => data_in(14), D => n790, Z => n798); U149 : AO2 port map( A => larray_5_15_port, B => n789, C => data_in(0), D => n790, Z => n799); U150 : AO2 port map( A => larray_5_14_port, B => n789, C => data_in(1), D => n790, Z => n800); U151 : AO2 port map( A => larray_5_13_port, B => n789, C => data_in(2), D => n790, Z => n801); U152 : AO2 port map( A => larray_5_12_port, B => n789, C => data_in(3), D => n790, Z => n802); U153 : AO2 port map( A => larray_5_11_port, B => n789, C => data_in(4), D => n790, Z => n803); U154 : AO2 port map( A => larray_5_10_port, B => n789, C => data_in(5), D => n790, Z => n804); U155 : AO2 port map( A => larray_5_0_port, B => n789, C => data_in(15), D => n790, Z => n805); U156 : AO2 port map( A => larray_4_9_port, B => n807, C => data_in(6), D => n808, Z => n806); U157 : AO2 port map( A => larray_4_8_port, B => n807, C => data_in(7), D => n808, Z => n809); U158 : AO2 port map( A => larray_4_7_port, B => n807, C => data_in(8), D => n808, Z => n810); U159 : AO2 port map( A => larray_4_6_port, B => n807, C => data_in(9), D => n808, Z => n811); U160 : AO2 port map( A => larray_4_5_port, B => n807, C => data_in(10), D => n808, Z => n812); U161 : AO2 port map( A => larray_4_4_port, B => n807, C => data_in(11), D => n808, Z => n813); U162 : AO2 port map( A => larray_4_3_port, B => n807, C => data_in(12), D => n808, Z => n814); U163 : AO2 port map( A => larray_4_2_port, B => n807, C => data_in(13), D => n808, Z => n815); U164 : AO2 port map( A => larray_4_1_port, B => n807, C => data_in(14), D => n808, Z => n816); U165 : AO2 port map( A => larray_4_15_port, B => n807, C => data_in(0), D => n808, Z => n817); U166 : AO2 port map( A => larray_4_14_port, B => n807, C => data_in(1), D => n808, Z => n818); U167 : AO2 port map( A => larray_4_13_port, B => n807, C => data_in(2), D => n808, Z => n819); U168 : AO2 port map( A => larray_4_12_port, B => n807, C => data_in(3), D => n808, Z => n820); U169 : AO2 port map( A => larray_4_11_port, B => n807, C => data_in(4), D => n808, Z => n821); U170 : AO2 port map( A => larray_4_10_port, B => n807, C => data_in(5), D => n808, Z => n822); U171 : AO2 port map( A => larray_4_0_port, B => n807, C => data_in(15), D => n808, Z => n823); U172 : AO2 port map( A => larray_3_9_port, B => n825, C => data_in(6), D => n826, Z => n824); U173 : AO2 port map( A => larray_3_8_port, B => n825, C => data_in(7), D => n826, Z => n827); U174 : AO2 port map( A => larray_3_7_port, B => n825, C => data_in(8), D => n826, Z => n828); U175 : AO2 port map( A => larray_3_6_port, B => n825, C => data_in(9), D => n826, Z => n829); U176 : AO2 port map( A => larray_3_5_port, B => n825, C => data_in(10), D => n826, Z => n830); U177 : AO2 port map( A => larray_3_4_port, B => n825, C => data_in(11), D => n826, Z => n831); U178 : AO2 port map( A => larray_3_3_port, B => n825, C => data_in(12), D => n826, Z => n832); U179 : AO2 port map( A => larray_3_2_port, B => n825, C => data_in(13), D => n826, Z => n833); U180 : AO2 port map( A => larray_3_1_port, B => n825, C => data_in(14), D => n826, Z => n834); U181 : AO2 port map( A => larray_3_15_port, B => n825, C => data_in(0), D => n826, Z => n835); U182 : AO2 port map( A => larray_3_14_port, B => n825, C => data_in(1), D => n826, Z => n836); U183 : AO2 port map( A => larray_3_13_port, B => n825, C => data_in(2), D => n826, Z => n837); U184 : AO2 port map( A => larray_3_12_port, B => n825, C => data_in(3), D => n826, Z => n838); U185 : AO2 port map( A => larray_3_11_port, B => n825, C => data_in(4), D => n826, Z => n839); U186 : AO2 port map( A => larray_3_10_port, B => n825, C => data_in(5), D => n826, Z => n840); U187 : AO2 port map( A => larray_3_0_port, B => n825, C => data_in(15), D => n826, Z => n841); U188 : AO2 port map( A => larray_2_9_port, B => n843, C => data_in(6), D => n844, Z => n842); U189 : AO2 port map( A => larray_2_8_port, B => n843, C => data_in(7), D => n844, Z => n845); U190 : AO2 port map( A => larray_2_7_port, B => n843, C => data_in(8), D => n844, Z => n846); U191 : AO2 port map( A => larray_2_6_port, B => n843, C => data_in(9), D => n844, Z => n847); U192 : AO2 port map( A => larray_2_5_port, B => n843, C => data_in(10), D => n844, Z => n848); U193 : AO2 port map( A => larray_2_4_port, B => n843, C => data_in(11), D => n844, Z => n849); U194 : AO2 port map( A => larray_2_3_port, B => n843, C => data_in(12), D => n844, Z => n850); U195 : AO2 port map( A => larray_2_2_port, B => n843, C => data_in(13), D => n844, Z => n851); U196 : AO2 port map( A => larray_2_1_port, B => n843, C => data_in(14), D => n844, Z => n852); U197 : AO2 port map( A => larray_2_15_port, B => n843, C => data_in(0), D => n844, Z => n853); U198 : AO2 port map( A => larray_2_14_port, B => n843, C => data_in(1), D => n844, Z => n854); U199 : AO2 port map( A => larray_2_13_port, B => n843, C => data_in(2), D => n844, Z => n855); U200 : AO2 port map( A => larray_2_12_port, B => n843, C => data_in(3), D => n844, Z => n856); U201 : AO2 port map( A => larray_2_11_port, B => n843, C => data_in(4), D => n844, Z => n857); U202 : AO2 port map( A => larray_2_10_port, B => n843, C => data_in(5), D => n844, Z => n858); U203 : AO2 port map( A => larray_2_0_port, B => n843, C => data_in(15), D => n844, Z => n859); U204 : AO2 port map( A => larray_1_9_port, B => n861, C => data_in(6), D => n862, Z => n860); U205 : AO2 port map( A => larray_1_8_port, B => n861, C => data_in(7), D => n862, Z => n863); U206 : AO2 port map( A => larray_1_7_port, B => n861, C => data_in(8), D => n862, Z => n864); U207 : AO2 port map( A => larray_1_6_port, B => n861, C => data_in(9), D => n862, Z => n865); U208 : AO2 port map( A => larray_1_5_port, B => n861, C => data_in(10), D => n862, Z => n866); U209 : AO2 port map( A => larray_1_4_port, B => n861, C => data_in(11), D => n862, Z => n867); U210 : AO2 port map( A => larray_1_3_port, B => n861, C => data_in(12), D => n862, Z => n868); U211 : AO2 port map( A => larray_1_2_port, B => n861, C => data_in(13), D => n862, Z => n869); U212 : AO2 port map( A => larray_1_1_port, B => n861, C => data_in(14), D => n862, Z => n870); U213 : AO2 port map( A => larray_1_15_port, B => n861, C => data_in(0), D => n862, Z => n871); U214 : AO2 port map( A => larray_1_14_port, B => n861, C => data_in(1), D => n862, Z => n872); U215 : AO2 port map( A => larray_1_13_port, B => n861, C => data_in(2), D => n862, Z => n873); U216 : AO2 port map( A => larray_1_12_port, B => n861, C => data_in(3), D => n862, Z => n874); U217 : AO2 port map( A => larray_1_11_port, B => n861, C => data_in(4), D => n862, Z => n875); U218 : AO2 port map( A => larray_1_10_port, B => n861, C => data_in(5), D => n862, Z => n876); U219 : AO2 port map( A => larray_1_0_port, B => n861, C => data_in(15), D => n862, Z => n877); U220 : AO2 port map( A => larray_0_9_port, B => n879, C => data_in(6), D => n880, Z => n878); U221 : AO2 port map( A => larray_0_8_port, B => n879, C => data_in(7), D => n880, Z => n881); U222 : AO2 port map( A => larray_0_7_port, B => n879, C => data_in(8), D => n880, Z => n882); U223 : AO2 port map( A => larray_0_6_port, B => n879, C => data_in(9), D => n880, Z => n883); U224 : AO2 port map( A => larray_0_5_port, B => n879, C => data_in(10), D => n880, Z => n884); U225 : AO2 port map( A => larray_0_4_port, B => n879, C => data_in(11), D => n880, Z => n885); U226 : AO2 port map( A => larray_0_3_port, B => n879, C => data_in(12), D => n880, Z => n886); U227 : AO2 port map( A => larray_0_2_port, B => n879, C => data_in(13), D => n880, Z => n887); U228 : AO2 port map( A => larray_0_1_port, B => n879, C => data_in(14), D => n880, Z => n888); U229 : AO2 port map( A => larray_0_15_port, B => n879, C => data_in(0), D => n880, Z => n889); U230 : AO2 port map( A => larray_0_14_port, B => n879, C => data_in(1), D => n880, Z => n890); U231 : AO2 port map( A => larray_0_13_port, B => n879, C => data_in(2), D => n880, Z => n891); U232 : AO2 port map( A => larray_0_12_port, B => n879, C => data_in(3), D => n880, Z => n892); U233 : AO2 port map( A => larray_0_11_port, B => n879, C => data_in(4), D => n880, Z => n893); U234 : AO2 port map( A => larray_0_10_port, B => n879, C => data_in(5), D => n880, Z => n894); U235 : AO2 port map( A => larray_0_0_port, B => n879, C => data_in(15), D => n880, Z => n895); U236 : AO2 port map( A => n732, B => larray_7_9_port, C => n733, D => larray_6_9_port, Z => n629); U237 : AO2 port map( A => n734, B => larray_5_9_port, C => n735, D => larray_4_9_port, Z => n628); U238 : AO2 port map( A => n736, B => larray_3_9_port, C => n737, D => larray_2_9_port, Z => n627); U239 : AO2 port map( A => n738, B => larray_1_9_port, C => n739, D => larray_0_9_port, Z => n626); U240 : AO2 port map( A => larray_7_8_port, B => n732, C => larray_6_8_port, D => n733, Z => n633); U241 : AO2 port map( A => larray_5_8_port, B => n734, C => larray_4_8_port, D => n735, Z => n632); U242 : AO2 port map( A => larray_3_8_port, B => n736, C => larray_2_8_port, D => n737, Z => n631); U243 : AO2 port map( A => larray_1_8_port, B => n738, C => larray_0_8_port, D => n739, Z => n630); U244 : AO2 port map( A => larray_7_7_port, B => n732, C => larray_6_7_port, D => n733, Z => n637); U245 : AO2 port map( A => larray_5_7_port, B => n734, C => larray_4_7_port, D => n735, Z => n636); U246 : AO2 port map( A => larray_3_7_port, B => n736, C => larray_2_7_port, D => n737, Z => n635); U247 : AO2 port map( A => larray_1_7_port, B => n738, C => larray_0_7_port, D => n739, Z => n634); U248 : AO2 port map( A => larray_7_6_port, B => n732, C => larray_6_6_port, D => n733, Z => n641); U249 : AO2 port map( A => larray_5_6_port, B => n734, C => larray_4_6_port, D => n735, Z => n640); U250 : AO2 port map( A => larray_3_6_port, B => n736, C => larray_2_6_port, D => n737, Z => n639); U251 : AO2 port map( A => larray_1_6_port, B => n738, C => larray_0_6_port, D => n739, Z => n638); U252 : AO2 port map( A => larray_7_5_port, B => n732, C => larray_6_5_port, D => n733, Z => n645); U253 : AO2 port map( A => larray_5_5_port, B => n734, C => larray_4_5_port, D => n735, Z => n644); U254 : AO2 port map( A => larray_3_5_port, B => n736, C => larray_2_5_port, D => n737, Z => n643); U255 : AO2 port map( A => larray_1_5_port, B => n738, C => larray_0_5_port, D => n739, Z => n642); U256 : AO2 port map( A => larray_7_4_port, B => n732, C => larray_6_4_port, D => n733, Z => n649); U257 : AO2 port map( A => larray_5_4_port, B => n734, C => larray_4_4_port, D => n735, Z => n648); U258 : AO2 port map( A => larray_3_4_port, B => n736, C => larray_2_4_port, D => n737, Z => n647); U259 : AO2 port map( A => larray_1_4_port, B => n738, C => larray_0_4_port, D => n739, Z => n646); U260 : AO2 port map( A => larray_7_3_port, B => n732, C => larray_6_3_port, D => n733, Z => n653); U261 : AO2 port map( A => larray_5_3_port, B => n734, C => larray_4_3_port, D => n735, Z => n652); U262 : AO2 port map( A => larray_3_3_port, B => n736, C => larray_2_3_port, D => n737, Z => n651); U263 : AO2 port map( A => larray_1_3_port, B => n738, C => larray_0_3_port, D => n739, Z => n650); U264 : AO2 port map( A => larray_7_2_port, B => n732, C => larray_6_2_port, D => n733, Z => n657); U265 : AO2 port map( A => larray_5_2_port, B => n734, C => larray_4_2_port, D => n735, Z => n656); U266 : AO2 port map( A => larray_3_2_port, B => n736, C => larray_2_2_port, D => n737, Z => n655); U267 : AO2 port map( A => larray_1_2_port, B => n738, C => larray_0_2_port, D => n739, Z => n654); U268 : AO2 port map( A => larray_7_1_port, B => n732, C => larray_6_1_port, D => n733, Z => n661); U269 : AO2 port map( A => larray_5_1_port, B => n734, C => larray_4_1_port, D => n735, Z => n660); U270 : AO2 port map( A => larray_3_1_port, B => n736, C => larray_2_1_port, D => n737, Z => n659); U271 : AO2 port map( A => larray_1_1_port, B => n738, C => larray_0_1_port, D => n739, Z => n658); U272 : AO2 port map( A => larray_7_15_port, B => n732, C => larray_6_15_port , D => n733, Z => n605); U273 : AO2 port map( A => larray_5_15_port, B => n734, C => larray_4_15_port , D => n735, Z => n604); U274 : AO2 port map( A => larray_3_15_port, B => n736, C => larray_2_15_port , D => n737, Z => n603); U275 : AO2 port map( A => larray_1_15_port, B => n738, C => larray_0_15_port , D => n739, Z => n602); U276 : AO2 port map( A => larray_7_14_port, B => n732, C => larray_6_14_port , D => n733, Z => n609); U277 : AO2 port map( A => larray_5_14_port, B => n734, C => larray_4_14_port , D => n735, Z => n608); U278 : AO2 port map( A => larray_3_14_port, B => n736, C => larray_2_14_port , D => n737, Z => n607); U279 : AO2 port map( A => larray_1_14_port, B => n738, C => larray_0_14_port , D => n739, Z => n606); U280 : AO2 port map( A => larray_7_13_port, B => n732, C => larray_6_13_port , D => n733, Z => n613); U281 : AO2 port map( A => larray_5_13_port, B => n734, C => larray_4_13_port , D => n735, Z => n612); U282 : AO2 port map( A => larray_3_13_port, B => n736, C => larray_2_13_port , D => n737, Z => n611); U283 : AO2 port map( A => larray_1_13_port, B => n738, C => larray_0_13_port , D => n739, Z => n610); U284 : AO2 port map( A => larray_7_12_port, B => n732, C => larray_6_12_port , D => n733, Z => n617); U285 : AO2 port map( A => larray_5_12_port, B => n734, C => larray_4_12_port , D => n735, Z => n616); U286 : AO2 port map( A => larray_3_12_port, B => n736, C => larray_2_12_port , D => n737, Z => n615); U287 : AO2 port map( A => larray_1_12_port, B => n738, C => larray_0_12_port , D => n739, Z => n614); U288 : AO2 port map( A => larray_7_11_port, B => n732, C => larray_6_11_port , D => n733, Z => n621); U289 : AO2 port map( A => larray_5_11_port, B => n734, C => larray_4_11_port , D => n735, Z => n620); U290 : AO2 port map( A => larray_3_11_port, B => n736, C => larray_2_11_port , D => n737, Z => n619); U291 : AO2 port map( A => larray_1_11_port, B => n738, C => larray_0_11_port , D => n739, Z => n618); U292 : AO2 port map( A => larray_7_10_port, B => n732, C => larray_6_10_port , D => n733, Z => n625); U293 : AO2 port map( A => larray_5_10_port, B => n734, C => larray_4_10_port , D => n735, Z => n624); U294 : AO2 port map( A => larray_3_10_port, B => n736, C => larray_2_10_port , D => n737, Z => n623); U295 : AO2 port map( A => larray_1_10_port, B => n738, C => larray_0_10_port , D => n739, Z => n622); U296 : AO2 port map( A => larray_7_0_port, B => n732, C => larray_6_0_port, D => n733, Z => n665); U297 : AO2 port map( A => larray_5_0_port, B => n734, C => larray_4_0_port, D => n735, Z => n664); U298 : AO2 port map( A => larray_3_0_port, B => n736, C => larray_2_0_port, D => n737, Z => n663); U299 : AO2 port map( A => larray_1_0_port, B => n738, C => larray_0_0_port, D => n739, Z => n662); U300 : AO2 port map( A => n742, B => larray_7_9_port, C => n743, D => larray_6_9_port, Z => n693); U301 : AO2 port map( A => n744, B => larray_5_9_port, C => n745, D => larray_4_9_port, Z => n692); U302 : AO2 port map( A => n746, B => larray_3_9_port, C => n747, D => larray_2_9_port, Z => n691); U303 : AO2 port map( A => n748, B => larray_1_9_port, C => n749, D => larray_0_9_port, Z => n690); U304 : AO2 port map( A => n742, B => larray_7_8_port, C => n743, D => larray_6_8_port, Z => n697); U305 : AO2 port map( A => n744, B => larray_5_8_port, C => n745, D => larray_4_8_port, Z => n696); U306 : AO2 port map( A => n746, B => larray_3_8_port, C => n747, D => larray_2_8_port, Z => n695); U307 : AO2 port map( A => n748, B => larray_1_8_port, C => n749, D => larray_0_8_port, Z => n694); U308 : AO2 port map( A => n742, B => larray_7_7_port, C => n743, D => larray_6_7_port, Z => n701); U309 : AO2 port map( A => n744, B => larray_5_7_port, C => n745, D => larray_4_7_port, Z => n700); U310 : AO2 port map( A => n746, B => larray_3_7_port, C => n747, D => larray_2_7_port, Z => n699); U311 : AO2 port map( A => n748, B => larray_1_7_port, C => n749, D => larray_0_7_port, Z => n698); U312 : AO2 port map( A => n742, B => larray_7_6_port, C => n743, D => larray_6_6_port, Z => n705); U313 : AO2 port map( A => n744, B => larray_5_6_port, C => n745, D => larray_4_6_port, Z => n704); U314 : AO2 port map( A => n746, B => larray_3_6_port, C => n747, D => larray_2_6_port, Z => n703); U315 : AO2 port map( A => n748, B => larray_1_6_port, C => n749, D => larray_0_6_port, Z => n702); U316 : AO2 port map( A => n742, B => larray_7_5_port, C => n743, D => larray_6_5_port, Z => n709); U317 : AO2 port map( A => n744, B => larray_5_5_port, C => n745, D => larray_4_5_port, Z => n708); U318 : AO2 port map( A => n746, B => larray_3_5_port, C => n747, D => larray_2_5_port, Z => n707); U319 : AO2 port map( A => n748, B => larray_1_5_port, C => n749, D => larray_0_5_port, Z => n706); U320 : AO2 port map( A => n742, B => larray_7_4_port, C => n743, D => larray_6_4_port, Z => n713); U321 : AO2 port map( A => n744, B => larray_5_4_port, C => n745, D => larray_4_4_port, Z => n712); U322 : AO2 port map( A => n746, B => larray_3_4_port, C => n747, D => larray_2_4_port, Z => n711); U323 : AO2 port map( A => n748, B => larray_1_4_port, C => n749, D => larray_0_4_port, Z => n710); U324 : AO2 port map( A => n742, B => larray_7_3_port, C => n743, D => larray_6_3_port, Z => n717); U325 : AO2 port map( A => n744, B => larray_5_3_port, C => n745, D => larray_4_3_port, Z => n716); U326 : AO2 port map( A => n746, B => larray_3_3_port, C => n747, D => larray_2_3_port, Z => n715); U327 : AO2 port map( A => n748, B => larray_1_3_port, C => n749, D => larray_0_3_port, Z => n714); U328 : AO2 port map( A => n742, B => larray_7_2_port, C => n743, D => larray_6_2_port, Z => n721); U329 : AO2 port map( A => n744, B => larray_5_2_port, C => n745, D => larray_4_2_port, Z => n720); U330 : AO2 port map( A => n746, B => larray_3_2_port, C => n747, D => larray_2_2_port, Z => n719); U331 : AO2 port map( A => n748, B => larray_1_2_port, C => n749, D => larray_0_2_port, Z => n718); U332 : AO2 port map( A => n742, B => larray_7_1_port, C => n743, D => larray_6_1_port, Z => n725); U333 : AO2 port map( A => n744, B => larray_5_1_port, C => n745, D => larray_4_1_port, Z => n724); U334 : AO2 port map( A => n746, B => larray_3_1_port, C => n747, D => larray_2_1_port, Z => n723); U335 : AO2 port map( A => n748, B => larray_1_1_port, C => n749, D => larray_0_1_port, Z => n722); U336 : AO2 port map( A => n742, B => larray_7_15_port, C => n743, D => larray_6_15_port, Z => n669); U337 : AO2 port map( A => n744, B => larray_5_15_port, C => n745, D => larray_4_15_port, Z => n668); U338 : AO2 port map( A => n746, B => larray_3_15_port, C => n747, D => larray_2_15_port, Z => n667); U339 : AO2 port map( A => n748, B => larray_1_15_port, C => n749, D => larray_0_15_port, Z => n666); U340 : AO2 port map( A => n742, B => larray_7_14_port, C => n743, D => larray_6_14_port, Z => n673); U341 : AO2 port map( A => n744, B => larray_5_14_port, C => n745, D => larray_4_14_port, Z => n672); U342 : AO2 port map( A => n746, B => larray_3_14_port, C => n747, D => larray_2_14_port, Z => n671); U343 : AO2 port map( A => n748, B => larray_1_14_port, C => n749, D => larray_0_14_port, Z => n670); U344 : AO2 port map( A => n742, B => larray_7_13_port, C => n743, D => larray_6_13_port, Z => n677); U345 : AO2 port map( A => n744, B => larray_5_13_port, C => n745, D => larray_4_13_port, Z => n676); U346 : AO2 port map( A => n746, B => larray_3_13_port, C => n747, D => larray_2_13_port, Z => n675); U347 : AO2 port map( A => n748, B => larray_1_13_port, C => n749, D => larray_0_13_port, Z => n674); U348 : AO2 port map( A => n742, B => larray_7_12_port, C => n743, D => larray_6_12_port, Z => n681); U349 : AO2 port map( A => n744, B => larray_5_12_port, C => n745, D => larray_4_12_port, Z => n680); U350 : AO2 port map( A => n746, B => larray_3_12_port, C => n747, D => larray_2_12_port, Z => n679); U351 : AO2 port map( A => n748, B => larray_1_12_port, C => n749, D => larray_0_12_port, Z => n678); U352 : AO2 port map( A => n742, B => larray_7_11_port, C => n743, D => larray_6_11_port, Z => n685); U353 : AO2 port map( A => n744, B => larray_5_11_port, C => n745, D => larray_4_11_port, Z => n684); U354 : AO2 port map( A => n746, B => larray_3_11_port, C => n747, D => larray_2_11_port, Z => n683); U355 : AO2 port map( A => n748, B => larray_1_11_port, C => n749, D => larray_0_11_port, Z => n682); U356 : AO2 port map( A => n742, B => larray_7_10_port, C => n743, D => larray_6_10_port, Z => n689); U357 : AO2 port map( A => n744, B => larray_5_10_port, C => n745, D => larray_4_10_port, Z => n688); U358 : AO2 port map( A => n746, B => larray_3_10_port, C => n747, D => larray_2_10_port, Z => n687); U359 : AO2 port map( A => n748, B => larray_1_10_port, C => n749, D => larray_0_10_port, Z => n686); U360 : AO2 port map( A => n742, B => larray_7_0_port, C => n743, D => larray_6_0_port, Z => n729); U361 : AO2 port map( A => n744, B => larray_5_0_port, C => n745, D => larray_4_0_port, Z => n728); U362 : AO2 port map( A => n746, B => larray_3_0_port, C => n747, D => larray_2_0_port, Z => n727); U363 : AO2 port map( A => n748, B => larray_1_0_port, C => n749, D => larray_0_0_port, Z => n726); U364 : AN3 port map( A => n750, B => n751, C => DR_address(0), Z => n808); U365 : AN3 port map( A => DR_address(2), B => n750, C => DR_address(0), Z => n790); U366 : AN3 port map( A => DR_address(1), B => n751, C => DR_address(0), Z => n772); U367 : AN3 port map( A => DR_address(2), B => DR_address(1), C => DR_address(0), Z => n754); U368 : NR3 port map( A => DR_address(0), B => DR_address(2), C => DR_address(1), Z => n880); U369 : NR3 port map( A => DR_address(1), B => DR_address(0), C => n751, Z => n862); U370 : NR3 port map( A => DR_address(2), B => DR_address(0), C => n750, Z => n844); U371 : NR3 port map( A => n750, B => DR_address(0), C => n751, Z => n826); U372 : IV port map( A => n754, Z => n753); U373 : IV port map( A => n772, Z => n771); U374 : IV port map( A => n790, Z => n789); U375 : IV port map( A => n808, Z => n807); U376 : IV port map( A => n826, Z => n825); U377 : IV port map( A => n844, Z => n843); U378 : IV port map( A => n862, Z => n861); U379 : IV port map( A => n880, Z => n879); U380 : IV port map( A => n752, Z => larray355_7_9_port); U381 : IV port map( A => n755, Z => larray355_7_8_port); U382 : IV port map( A => n756, Z => larray355_7_7_port); U383 : IV port map( A => n757, Z => larray355_7_6_port); U384 : IV port map( A => n758, Z => larray355_7_5_port); U385 : IV port map( A => n759, Z => larray355_7_4_port); U386 : IV port map( A => n760, Z => larray355_7_3_port); U387 : IV port map( A => n761, Z => larray355_7_2_port); U388 : IV port map( A => n762, Z => larray355_7_1_port); U389 : IV port map( A => n763, Z => larray355_7_15_port); U390 : IV port map( A => n764, Z => larray355_7_14_port); U391 : IV port map( A => n765, Z => larray355_7_13_port); U392 : IV port map( A => n766, Z => larray355_7_12_port); U393 : IV port map( A => n767, Z => larray355_7_11_port); U394 : IV port map( A => n768, Z => larray355_7_10_port); U395 : IV port map( A => n769, Z => larray355_7_0_port); U396 : IV port map( A => n770, Z => larray355_6_9_port); U397 : IV port map( A => n773, Z => larray355_6_8_port); U398 : IV port map( A => n774, Z => larray355_6_7_port); U399 : IV port map( A => n775, Z => larray355_6_6_port); U400 : IV port map( A => n776, Z => larray355_6_5_port); U401 : IV port map( A => n777, Z => larray355_6_4_port); U402 : IV port map( A => n778, Z => larray355_6_3_port); U403 : IV port map( A => n779, Z => larray355_6_2_port); U404 : IV port map( A => n780, Z => larray355_6_1_port); U405 : IV port map( A => n781, Z => larray355_6_15_port); U406 : IV port map( A => n782, Z => larray355_6_14_port); U407 : IV port map( A => n783, Z => larray355_6_13_port); U408 : IV port map( A => n784, Z => larray355_6_12_port); U409 : IV port map( A => n785, Z => larray355_6_11_port); U410 : IV port map( A => n786, Z => larray355_6_10_port); U411 : IV port map( A => n787, Z => larray355_6_0_port); U412 : IV port map( A => n788, Z => larray355_5_9_port); U413 : IV port map( A => n791, Z => larray355_5_8_port); U414 : IV port map( A => n792, Z => larray355_5_7_port); U415 : IV port map( A => n793, Z => larray355_5_6_port); U416 : IV port map( A => n794, Z => larray355_5_5_port); U417 : IV port map( A => n795, Z => larray355_5_4_port); U418 : IV port map( A => n796, Z => larray355_5_3_port); U419 : IV port map( A => n797, Z => larray355_5_2_port); U420 : IV port map( A => n798, Z => larray355_5_1_port); U421 : IV port map( A => n799, Z => larray355_5_15_port); U422 : IV port map( A => n800, Z => larray355_5_14_port); U423 : IV port map( A => n801, Z => larray355_5_13_port); U424 : IV port map( A => n802, Z => larray355_5_12_port); U425 : IV port map( A => n803, Z => larray355_5_11_port); U426 : IV port map( A => n804, Z => larray355_5_10_port); U427 : IV port map( A => n805, Z => larray355_5_0_port); U428 : IV port map( A => n806, Z => larray355_4_9_port); U429 : IV port map( A => n809, Z => larray355_4_8_port); U430 : IV port map( A => n810, Z => larray355_4_7_port); U431 : IV port map( A => n811, Z => larray355_4_6_port); U432 : IV port map( A => n812, Z => larray355_4_5_port); U433 : IV port map( A => n813, Z => larray355_4_4_port); U434 : IV port map( A => n814, Z => larray355_4_3_port); U435 : IV port map( A => n815, Z => larray355_4_2_port); U436 : IV port map( A => n816, Z => larray355_4_1_port); U437 : IV port map( A => n817, Z => larray355_4_15_port); U438 : IV port map( A => n818, Z => larray355_4_14_port); U439 : IV port map( A => n819, Z => larray355_4_13_port); U440 : IV port map( A => n820, Z => larray355_4_12_port); U441 : IV port map( A => n821, Z => larray355_4_11_port); U442 : IV port map( A => n822, Z => larray355_4_10_port); U443 : IV port map( A => n823, Z => larray355_4_0_port); U444 : IV port map( A => n824, Z => larray355_3_9_port); U445 : IV port map( A => n827, Z => larray355_3_8_port); U446 : IV port map( A => n828, Z => larray355_3_7_port); U447 : IV port map( A => n829, Z => larray355_3_6_port); U448 : IV port map( A => n830, Z => larray355_3_5_port); U449 : IV port map( A => n831, Z => larray355_3_4_port); U450 : IV port map( A => n832, Z => larray355_3_3_port); U451 : IV port map( A => n833, Z => larray355_3_2_port); U452 : IV port map( A => n834, Z => larray355_3_1_port); U453 : IV port map( A => n835, Z => larray355_3_15_port); U454 : IV port map( A => n836, Z => larray355_3_14_port); U455 : IV port map( A => n837, Z => larray355_3_13_port); U456 : IV port map( A => n838, Z => larray355_3_12_port); U457 : IV port map( A => n839, Z => larray355_3_11_port); U458 : IV port map( A => n840, Z => larray355_3_10_port); U459 : IV port map( A => n841, Z => larray355_3_0_port); U460 : IV port map( A => n842, Z => larray355_2_9_port); U461 : IV port map( A => n845, Z => larray355_2_8_port); U462 : IV port map( A => n846, Z => larray355_2_7_port); U463 : IV port map( A => n847, Z => larray355_2_6_port); U464 : IV port map( A => n848, Z => larray355_2_5_port); U465 : IV port map( A => n849, Z => larray355_2_4_port); U466 : IV port map( A => n850, Z => larray355_2_3_port); U467 : IV port map( A => n851, Z => larray355_2_2_port); U468 : IV port map( A => n852, Z => larray355_2_1_port); U469 : IV port map( A => n853, Z => larray355_2_15_port); U470 : IV port map( A => n854, Z => larray355_2_14_port); U471 : IV port map( A => n855, Z => larray355_2_13_port); U472 : IV port map( A => n856, Z => larray355_2_12_port); U473 : IV port map( A => n857, Z => larray355_2_11_port); U474 : IV port map( A => n858, Z => larray355_2_10_port); U475 : IV port map( A => n859, Z => larray355_2_0_port); U476 : IV port map( A => n860, Z => larray355_1_9_port); U477 : IV port map( A => n863, Z => larray355_1_8_port); U478 : IV port map( A => n864, Z => larray355_1_7_port); U479 : IV port map( A => n865, Z => larray355_1_6_port); U480 : IV port map( A => n866, Z => larray355_1_5_port); U481 : IV port map( A => n867, Z => larray355_1_4_port); U482 : IV port map( A => n868, Z => larray355_1_3_port); U483 : IV port map( A => n869, Z => larray355_1_2_port); U484 : IV port map( A => n870, Z => larray355_1_1_port); U485 : IV port map( A => n871, Z => larray355_1_15_port); U486 : IV port map( A => n872, Z => larray355_1_14_port); U487 : IV port map( A => n873, Z => larray355_1_13_port); U488 : IV port map( A => n874, Z => larray355_1_12_port); U489 : IV port map( A => n875, Z => larray355_1_11_port); U490 : IV port map( A => n876, Z => larray355_1_10_port); U491 : IV port map( A => n877, Z => larray355_1_0_port); U492 : IV port map( A => n878, Z => larray355_0_9_port); U493 : IV port map( A => n881, Z => larray355_0_8_port); U494 : IV port map( A => n882, Z => larray355_0_7_port); U495 : IV port map( A => n883, Z => larray355_0_6_port); U496 : IV port map( A => n884, Z => larray355_0_5_port); U497 : IV port map( A => n885, Z => larray355_0_4_port); U498 : IV port map( A => n886, Z => larray355_0_3_port); U499 : IV port map( A => n887, Z => larray355_0_2_port); U500 : IV port map( A => n888, Z => larray355_0_1_port); U501 : IV port map( A => n889, Z => larray355_0_15_port); U502 : IV port map( A => n890, Z => larray355_0_14_port); U503 : IV port map( A => n891, Z => larray355_0_13_port); U504 : IV port map( A => n892, Z => larray355_0_12_port); U505 : IV port map( A => n893, Z => larray355_0_11_port); U506 : IV port map( A => n894, Z => larray355_0_10_port); U507 : IV port map( A => n895, Z => larray355_0_0_port); n896 <= '1'; n897 <= '1'; n898 <= '1'; n899 <= '1'; n900 <= '1'; n901 <= '1'; n902 <= '1'; n903 <= '1'; n904 <= '1'; n905 <= '1'; n906 <= '1'; n907 <= '1'; n908 <= '1'; n909 <= '1'; n910 <= '1'; n911 <= '1'; n912 <= '1'; n913 <= '1'; n914 <= '1'; n915 <= '1'; n916 <= '1'; n917 <= '1'; n918 <= '1'; n919 <= '1'; n920 <= '1'; n921 <= '1'; n922 <= '1'; n923 <= '1'; n924 <= '1'; n925 <= '1'; n926 <= '1'; n927 <= '1'; n928 <= '1'; n929 <= '1'; n930 <= '1'; n931 <= '1'; n932 <= '1'; n933 <= '1'; n934 <= '1'; n935 <= '1'; n936 <= '1'; n937 <= '1'; n938 <= '1'; n939 <= '1'; n940 <= '1'; n941 <= '1'; n942 <= '1'; n943 <= '1'; n944 <= '1'; n945 <= '1'; n946 <= '1'; n947 <= '1'; n948 <= '1'; n949 <= '1'; n950 <= '1'; n951 <= '1'; n952 <= '1'; n953 <= '1'; n954 <= '1'; n955 <= '1'; n956 <= '1'; n957 <= '1'; n958 <= '1'; n959 <= '1'; n960 <= '1'; n961 <= '1'; n962 <= '1'; n963 <= '1'; n964 <= '1'; n965 <= '1'; n966 <= '1'; n967 <= '1'; n968 <= '1'; n969 <= '1'; n970 <= '1'; n971 <= '1'; n972 <= '1'; n973 <= '1'; n974 <= '1'; n975 <= '1'; n976 <= '1'; n977 <= '1'; n978 <= '1'; n979 <= '1'; n980 <= '1'; n981 <= '1'; n982 <= '1'; n983 <= '1'; n984 <= '1'; n985 <= '1'; n986 <= '1'; n987 <= '1'; n988 <= '1'; n989 <= '1'; n990 <= '1'; n991 <= '1'; n992 <= '1'; n993 <= '1'; n994 <= '1'; n995 <= '1'; n996 <= '1'; n997 <= '1'; n998 <= '1'; n999 <= '1'; n1000 <= '1'; n1001 <= '1'; n1002 <= '1'; n1003 <= '1'; n1004 <= '1'; n1005 <= '1'; n1006 <= '1'; n1007 <= '1'; n1008 <= '1'; n1009 <= '1'; n1010 <= '1'; n1011 <= '1'; n1012 <= '1'; n1013 <= '1'; n1014 <= '1'; n1015 <= '1'; n1016 <= '1'; n1017 <= '1'; n1018 <= '1'; n1019 <= '1'; n1020 <= '1'; n1021 <= '1'; n1022 <= '1'; n1023 <= '1'; end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity LC2_ALU_DW01_add_16_0 is port( A, B : in std_logic_vector (0 to 15); CI : in std_logic; SUM : out std_logic_vector (0 to 15); CO : out std_logic); end LC2_ALU_DW01_add_16_0; architecture SYN of LC2_ALU_DW01_add_16_0 is component EO3P port( A, B, C : in std_logic; Z : out std_logic); end component; component FA1A port( CI, A, B : in std_logic; S, CO : out std_logic); end component; component AN2 port( A, B : in std_logic; Z : out std_logic); end component; component EO port( A, B : in std_logic; Z : out std_logic); end component; signal carry_9_port, carry_4_port, carry_2_port, carry_15_port, carry_13_port, carry_6_port, carry_14_port, carry_11_port, carry_10_port, carry_12_port, carry_8_port, carry_7_port, carry_3_port, carry_5_port, carry_1_port : std_logic; begin U1_15 : EO3P port map( A => A(0), B => B(0), C => carry_15_port, Z => SUM(0) ); U1_14 : FA1A port map( CI => carry_14_port, A => A(1), B => B(1), S => SUM(1), CO => carry_15_port); U1_13 : FA1A port map( CI => carry_13_port, A => A(2), B => B(2), S => SUM(2), CO => carry_14_port); U1_12 : FA1A port map( CI => carry_12_port, A => A(3), B => B(3), S => SUM(3), CO => carry_13_port); U1_11 : FA1A port map( CI => carry_11_port, A => A(4), B => B(4), S => SUM(4), CO => carry_12_port); U1_10 : FA1A port map( CI => carry_10_port, A => A(5), B => B(5), S => SUM(5), CO => carry_11_port); U1_9 : FA1A port map( CI => carry_9_port, A => A(6), B => B(6), S => SUM(6), CO => carry_10_port); U1_8 : FA1A port map( CI => carry_8_port, A => A(7), B => B(7), S => SUM(7), CO => carry_9_port); U1_7 : FA1A port map( CI => carry_7_port, A => A(8), B => B(8), S => SUM(8), CO => carry_8_port); U1_6 : FA1A port map( CI => carry_6_port, A => A(9), B => B(9), S => SUM(9), CO => carry_7_port); U1_5 : FA1A port map( CI => carry_5_port, A => A(10), B => B(10), S => SUM(10), CO => carry_6_port); U1_4 : FA1A port map( CI => carry_4_port, A => A(11), B => B(11), S => SUM(11), CO => carry_5_port); U1_3 : FA1A port map( CI => carry_3_port, A => A(12), B => B(12), S => SUM(12), CO => carry_4_port); U1_2 : FA1A port map( CI => carry_2_port, A => A(13), B => B(13), S => SUM(13), CO => carry_3_port); U1_1 : FA1A port map( CI => carry_1_port, A => A(14), B => B(14), S => SUM(14), CO => carry_2_port); U4 : AN2 port map( A => B(15), B => A(15), Z => carry_1_port); U5 : EO port map( A => A(15), B => B(15), Z => SUM(15)); end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity LC2_ALU is port( A, B : in std_logic_vector (0 to 15); S : in std_logic_vector (0 to 1); O : out std_logic_vector (0 to 15)); end LC2_ALU; architecture SYN of LC2_ALU is component ND2 port( A, B : in std_logic; Z : out std_logic); end component; component NR2 port( A, B : in std_logic; Z : out std_logic); end component; component IV port( A : in std_logic; Z : out std_logic); end component; component AN2 port( A, B : in std_logic; Z : out std_logic); end component; component AO2 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component LC2_ALU_DW01_add_16_0 port( A, B : in std_logic_vector (0 to 15); CI : in std_logic; SUM : out std_logic_vector (0 to 15); CO : out std_logic); end component; signal X_return86_13_port, X_return86_15_port, X_return86_11_port, X_return86_7_port, X_return86_3_port, X_return86_8_port, X_return86_1_port, X_return86_5_port, X_return86_4_port, X_return86_9_port, X_return86_0_port, X_return86_2_port, X_return86_6_port, X_return86_10_port, X_return86_14_port, X_return86_12_port, n599, n600, n601, n1024, n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106 : std_logic; begin U26 : ND2 port map( A => n599, B => n600, Z => O(0)); U27 : ND2 port map( A => n601, B => n1024, Z => O(1)); U28 : ND2 port map( A => n1025, B => n1026, Z => O(2)); U29 : ND2 port map( A => n1027, B => n1028, Z => O(3)); U30 : ND2 port map( A => n1029, B => n1030, Z => O(4)); U31 : ND2 port map( A => n1031, B => n1032, Z => O(5)); U32 : ND2 port map( A => n1033, B => n1034, Z => O(6)); U33 : ND2 port map( A => n1035, B => n1036, Z => O(7)); U34 : ND2 port map( A => n1037, B => n1038, Z => O(8)); U35 : ND2 port map( A => n1039, B => n1040, Z => O(9)); U36 : ND2 port map( A => n1041, B => n1042, Z => O(10)); U37 : ND2 port map( A => n1043, B => n1044, Z => O(11)); U38 : ND2 port map( A => n1045, B => n1046, Z => O(12)); U39 : ND2 port map( A => n1047, B => n1048, Z => O(13)); U40 : ND2 port map( A => n1049, B => n1050, Z => O(14)); U41 : ND2 port map( A => n1051, B => n1052, Z => O(15)); U42 : NR2 port map( A => S(1), B => S(0), Z => n1053); U43 : IV port map( A => S(1), Z => n1054); U44 : NR2 port map( A => n1054, B => S(0), Z => n1055); U45 : ND2 port map( A => n1057, B => n1058, Z => n1056); U46 : ND2 port map( A => n1057, B => n1060, Z => n1059); U47 : ND2 port map( A => n1057, B => n1062, Z => n1061); U48 : ND2 port map( A => n1057, B => n1064, Z => n1063); U49 : ND2 port map( A => n1057, B => n1066, Z => n1065); U50 : ND2 port map( A => n1057, B => n1068, Z => n1067); U51 : ND2 port map( A => n1057, B => n1070, Z => n1069); U52 : ND2 port map( A => n1057, B => n1072, Z => n1071); U53 : ND2 port map( A => n1057, B => n1074, Z => n1073); U54 : ND2 port map( A => n1057, B => n1076, Z => n1075); U55 : ND2 port map( A => n1057, B => n1078, Z => n1077); U56 : ND2 port map( A => n1057, B => n1080, Z => n1079); U57 : ND2 port map( A => n1057, B => n1082, Z => n1081); U58 : ND2 port map( A => n1057, B => n1084, Z => n1083); U59 : ND2 port map( A => n1057, B => n1086, Z => n1085); U60 : ND2 port map( A => n1057, B => n1088, Z => n1087); U61 : ND2 port map( A => S(0), B => n1054, Z => n1057); U62 : AN2 port map( A => S(0), B => S(1), Z => n1089); U63 : ND2 port map( A => n1055, B => B(6), Z => n1058); U64 : ND2 port map( A => n1053, B => X_return86_9_port, Z => n1034); U65 : ND2 port map( A => B(7), B => n1055, Z => n1060); U66 : ND2 port map( A => X_return86_8_port, B => n1053, Z => n1036); U67 : ND2 port map( A => B(8), B => n1055, Z => n1062); U68 : ND2 port map( A => X_return86_7_port, B => n1053, Z => n1038); U69 : ND2 port map( A => B(9), B => n1055, Z => n1064); U70 : ND2 port map( A => X_return86_6_port, B => n1053, Z => n1040); U71 : ND2 port map( A => B(10), B => n1055, Z => n1066); U72 : ND2 port map( A => X_return86_5_port, B => n1053, Z => n1042); U73 : ND2 port map( A => B(11), B => n1055, Z => n1068); U74 : ND2 port map( A => X_return86_4_port, B => n1053, Z => n1044); U75 : ND2 port map( A => B(12), B => n1055, Z => n1070); U76 : ND2 port map( A => X_return86_3_port, B => n1053, Z => n1046); U77 : ND2 port map( A => B(13), B => n1055, Z => n1072); U78 : ND2 port map( A => X_return86_2_port, B => n1053, Z => n1048); U79 : ND2 port map( A => B(14), B => n1055, Z => n1074); U80 : ND2 port map( A => X_return86_1_port, B => n1053, Z => n1050); U81 : ND2 port map( A => B(0), B => n1055, Z => n1076); U82 : ND2 port map( A => X_return86_15_port, B => n1053, Z => n600); U83 : ND2 port map( A => B(1), B => n1055, Z => n1078); U84 : ND2 port map( A => X_return86_14_port, B => n1053, Z => n1024); U85 : ND2 port map( A => B(2), B => n1055, Z => n1080); U86 : ND2 port map( A => X_return86_13_port, B => n1053, Z => n1026); U87 : ND2 port map( A => B(3), B => n1055, Z => n1082); U88 : ND2 port map( A => X_return86_12_port, B => n1053, Z => n1028); U89 : ND2 port map( A => B(4), B => n1055, Z => n1084); U90 : ND2 port map( A => X_return86_11_port, B => n1053, Z => n1030); U91 : ND2 port map( A => B(5), B => n1055, Z => n1086); U92 : ND2 port map( A => X_return86_10_port, B => n1053, Z => n1032); U93 : ND2 port map( A => B(15), B => n1055, Z => n1088); U94 : ND2 port map( A => X_return86_0_port, B => n1053, Z => n1052); U95 : AO2 port map( A => n1089, B => n1090, C => n1056, D => A(6), Z => n1033); U96 : AO2 port map( A => n1089, B => n1091, C => n1059, D => A(7), Z => n1035); U97 : AO2 port map( A => n1089, B => n1092, C => n1061, D => A(8), Z => n1037); U98 : AO2 port map( A => n1089, B => n1093, C => n1063, D => A(9), Z => n1039); U99 : AO2 port map( A => n1089, B => n1094, C => n1065, D => A(10), Z => n1041); U100 : AO2 port map( A => n1089, B => n1095, C => n1067, D => A(11), Z => n1043); U101 : AO2 port map( A => n1089, B => n1096, C => n1069, D => A(12), Z => n1045); U102 : AO2 port map( A => n1089, B => n1097, C => n1071, D => A(13), Z => n1047); U103 : AO2 port map( A => n1089, B => n1098, C => n1073, D => A(14), Z => n1049); U104 : AO2 port map( A => n1089, B => n1099, C => n1075, D => A(0), Z => n599); U105 : AO2 port map( A => n1089, B => n1100, C => n1077, D => A(1), Z => n601); U106 : AO2 port map( A => n1089, B => n1101, C => n1079, D => A(2), Z => n1025); U107 : AO2 port map( A => n1089, B => n1102, C => n1081, D => A(3), Z => n1027); U108 : AO2 port map( A => n1089, B => n1103, C => n1083, D => A(4), Z => n1029); U109 : AO2 port map( A => n1089, B => n1104, C => n1085, D => A(5), Z => n1031); U110 : AO2 port map( A => n1089, B => n1105, C => n1087, D => A(15), Z => n1051); U111 : IV port map( A => A(6), Z => n1090); U112 : IV port map( A => A(7), Z => n1091); U113 : IV port map( A => A(8), Z => n1092); U114 : IV port map( A => A(9), Z => n1093); U115 : IV port map( A => A(10), Z => n1094); U116 : IV port map( A => A(11), Z => n1095); U117 : IV port map( A => A(12), Z => n1096); U118 : IV port map( A => A(13), Z => n1097); U119 : IV port map( A => A(14), Z => n1098); U120 : IV port map( A => A(0), Z => n1099); U121 : IV port map( A => A(1), Z => n1100); U122 : IV port map( A => A(2), Z => n1101); U123 : IV port map( A => A(3), Z => n1102); U124 : IV port map( A => A(4), Z => n1103); U125 : IV port map( A => A(5), Z => n1104); U126 : IV port map( A => A(15), Z => n1105); add_47_plus_plus : LC2_ALU_DW01_add_16_0 port map( A(0) => A(0), A(1) => A(1), A(2) => A(2), A(3) => A(3), A(4) => A(4), A(5) => A(5), A(6) => A(6), A(7) => A(7), A(8) => A(8), A(9) => A(9), A(10) => A(10), A(11) => A(11), A(12) => A(12), A(13) => A(13), A(14) => A(14), A(15) => A(15), B(0) => B(0), B(1) => B(1), B(2) => B(2), B(3) => B(3), B(4) => B(4), B(5) => B(5), B(6) => B(6), B(7) => B(7), B(8) => B(8), B(9) => B(9), B(10) => B(10), B(11) => B(11), B(12) => B(12), B(13) => B(13), B(14) => B(14), B(15) => B(15), CI => n1106, SUM(0) => X_return86_15_port, SUM(1) => X_return86_14_port, SUM(2) => X_return86_13_port, SUM(3) => X_return86_12_port, SUM(4) => X_return86_11_port, SUM(5) => X_return86_10_port, SUM(6) => X_return86_9_port, SUM(7) => X_return86_8_port, SUM(8) => X_return86_7_port, SUM(9) => X_return86_6_port, SUM(10) => X_return86_5_port, SUM(11) => X_return86_4_port, SUM(12) => X_return86_3_port, SUM(13) => X_return86_2_port, SUM(14) => X_return86_1_port, SUM(15) => X_return86_0_port, CO => open); n1106 <= '0'; end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity mem_logic is port( read_write : in std_logic; MAR : in std_logic_vector (0 to 15); MIO_enable : in std_logic; mem_enable : out std_logic; mux_sel_out : out std_logic_vector (0 to 1); KBSR_ld, CRTDR_ld, CRTSR_ld : out std_logic); end mem_logic; architecture SYN of mem_logic is component LD2 port( D, GN : in std_logic; Q, QN : out std_logic); end component; component AO7 port( A, B, C : in std_logic; Z : out std_logic); end component; component AN3 port( A, B, C : in std_logic; Z : out std_logic); end component; component AN4 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component AO6 port( A, B, C : in std_logic; Z : out std_logic); end component; component IV port( A : in std_logic; Z : out std_logic); end component; component OR4 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component ND4 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component NR2 port( A, B : in std_logic; Z : out std_logic); end component; component ND2 port( A, B : in std_logic; Z : out std_logic); end component; component OR3 port( A, B, C : in std_logic; Z : out std_logic); end component; component AO2 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component NR4 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component AO4 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component EO1 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component EON1 port( A, B, C, D : in std_logic; Z : out std_logic); end component; signal n_540, n_539, n84, n85, n290, n291, n292, n293, n294, n295, n296, n297, n298, n299, n300, n301, n302, n303, n304, n305, n306, n307, n308, n309, n310, n311, n312, n313, n314, n315, n316, n317, n318, n319, n320, n321, n322, n323, n324 : std_logic; begin mux_sel_out_reg_1_label : LD2 port map( D => n_539, GN => n324, Q => mux_sel_out(0), QN => open); mux_sel_out_reg_0_label : LD2 port map( D => n_540, GN => n324, Q => mux_sel_out(1), QN => open); U42 : AO7 port map( A => MAR(15), B => n84, C => n85, Z => n_540); U43 : AO7 port map( A => n290, B => n291, C => n85, Z => n_539); U44 : AN3 port map( A => n292, B => n293, C => n294, Z => KBSR_ld); U45 : AN4 port map( A => n294, B => MAR(14), C => MAR(15), D => n295, Z => CRTDR_ld); U46 : AN3 port map( A => n296, B => n294, C => n295, Z => CRTSR_ld); U47 : AO6 port map( A => read_write, B => n292, C => n297, Z => n324); U48 : IV port map( A => MAR(3), Z => n298); U49 : IV port map( A => MAR(5), Z => n299); U50 : IV port map( A => MAR(8), Z => n300); U51 : IV port map( A => MAR(15), Z => n293); U52 : IV port map( A => MAR(10), Z => n301); U53 : IV port map( A => MAR(9), Z => n302); U54 : AN4 port map( A => MAR(0), B => MAR(1), C => n304, D => MAR(2), Z => n303); U55 : OR4 port map( A => n299, B => MAR(14), C => n305, D => n306, Z => n84) ; U56 : ND4 port map( A => n308, B => n303, C => n309, D => n310, Z => n307); U57 : IV port map( A => MAR(6), Z => n311); U58 : NR2 port map( A => MAR(15), B => MAR(14), Z => n296); U59 : ND4 port map( A => MAR(13), B => MAR(7), C => n312, D => n313, Z => n291); U60 : ND2 port map( A => MIO_enable, B => n303, Z => n314); U61 : NR2 port map( A => n314, B => n84, Z => n292); U62 : NR2 port map( A => n314, B => n291, Z => n295); U63 : IV port map( A => read_write, Z => n294); U64 : ND2 port map( A => MIO_enable, B => n307, Z => n315); U65 : NR2 port map( A => MAR(6), B => MAR(14), Z => n316); U66 : AO7 port map( A => MAR(14), B => n293, C => MAR(7), Z => n317); U67 : NR2 port map( A => MAR(7), B => MAR(6), Z => n318); U68 : ND4 port map( A => n300, B => n318, C => n302, D => n301, Z => n306); U69 : OR3 port map( A => MAR(13), B => MAR(11), C => MAR(12), Z => n305); U70 : NR2 port map( A => MAR(4), B => n298, Z => n304); U71 : AO2 port map( A => MAR(14), B => n293, C => MAR(8), D => n311, Z => n309); U72 : AN3 port map( A => n319, B => n320, C => n321, Z => n310); U73 : AN3 port map( A => MAR(11), B => n299, C => MAR(8), Z => n312); U74 : NR4 port map( A => n322, B => n301, C => n302, D => n311, Z => n313); U75 : ND2 port map( A => n295, B => n296, Z => n323); U76 : AO4 port map( A => n294, B => n315, C => n294, D => n323, Z => n297); U77 : IV port map( A => n315, Z => mem_enable); U78 : AO2 port map( A => MAR(11), B => MAR(5), C => n300, D => n299, Z => n320); U79 : EO1 port map( A => n317, B => MAR(13), C => n316, D => MAR(13), Z => n308); U80 : AO2 port map( A => MAR(7), B => n322, C => n302, D => MAR(12), Z => n319); U81 : EON1 port map( A => MAR(9), B => MAR(10), C => MAR(11), D => MAR(10), Z => n321); U82 : IV port map( A => n307, Z => n85); U83 : IV port map( A => n296, Z => n290); U84 : IV port map( A => MAR(12), Z => n322); end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity sext is port( A : in std_logic_vector (0 to 4); O : out std_logic_vector (0 to 15) ); end sext; architecture SYN of sext is begin O <= ( A(0), A(0), A(0), A(0), A(0), A(0), A(0), A(0), A(0), A(0), A(0), A(0), A(1), A(2), A(3), A(4) ); end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity NZP_logic is port( data : in std_logic_vector (0 to 15); O : out std_logic_vector (0 to 2)); end NZP_logic; architecture SYN of NZP_logic is component LD1 port( D, G : in std_logic; Q, QN : out std_logic); end component; component NR2 port( A, B : in std_logic; Z : out std_logic); end component; component NR4 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component AN4 port( A, B, C, D : in std_logic; Z : out std_logic); end component; signal n505, n506, n507, n508, n509, X_cell_1759_U1_CONTROL2, X_cell_1759_U1_CONTROL3 : std_logic; begin O_reg_2_label : LD1 port map( D => data(0), G => n505, Q => O(0), QN => open ); O_reg_1_label : LD1 port map( D => X_cell_1759_U1_CONTROL3, G => n505, Q => O(1), QN => open); O_reg_0_label : LD1 port map( D => X_cell_1759_U1_CONTROL2, G => n505, Q => O(2), QN => open); U103 : NR2 port map( A => data(0), B => X_cell_1759_U1_CONTROL3, Z => X_cell_1759_U1_CONTROL2); n505 <= '1'; U105 : NR4 port map( A => data(11), B => data(12), C => data(4), D => data(13), Z => n506); U106 : NR4 port map( A => data(5), B => data(10), C => data(0), D => data(8) , Z => n507); U107 : NR4 port map( A => data(15), B => data(6), C => data(3), D => data(14), Z => n508); U108 : NR4 port map( A => data(7), B => data(2), C => data(1), D => data(9), Z => n509); U109 : AN4 port map( A => n509, B => n508, C => n507, D => n506, Z => X_cell_1759_U1_CONTROL3); end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity NZP_reg is port( clk, load : in std_logic; data : in std_logic_vector (0 to 2); O : out std_logic_vector (0 to 2); clear : in std_logic); end NZP_reg; architecture SYN of NZP_reg is component FJK2S port( J, K, CP, CD, TI, TE : in std_logic; Q, QN : out std_logic); end component; component FD1 port( D, CP : in std_logic; Q, QN : out std_logic); end component; component AO7 port( A, B, C : in std_logic; Z : out std_logic); end component; component IV port( A : in std_logic; Z : out std_logic); end component; component NR2 port( A, B : in std_logic; Z : out std_logic); end component; component AN2 port( A, B : in std_logic; Z : out std_logic); end component; component AO2 port( A, B, C, D : in std_logic; Z : out std_logic); end component; signal temp_2_port, O39_1_port, temp_0_port, O39_2_port, temp_1_port, O39_0_port, n493, n494, n495, n496, n497, n498, n499, n500, n501, n502, n503, n504 : std_logic; begin temp_reg_2_label : FJK2S port map( J => n498, K => n498, CP => clk, CD => n500, TI => data(0), TE => load, Q => temp_2_port, QN => open); temp_reg_1_label : FJK2S port map( J => n499, K => n499, CP => clk, CD => n500, TI => data(1), TE => load, Q => temp_1_port, QN => open); temp_reg_0_label : FJK2S port map( J => n501, K => n501, CP => clk, CD => n500, TI => data(2), TE => load, Q => temp_0_port, QN => open); O_reg_2_label : FD1 port map( D => O39_2_port, CP => clk, Q => O(0), QN => n502); O_reg_1_label : FD1 port map( D => O39_1_port, CP => clk, Q => O(1), QN => n503); O_reg_0_label : FD1 port map( D => O39_0_port, CP => clk, Q => O(2), QN => n504); U25 : AO7 port map( A => n500, B => n502, C => n493, Z => O39_2_port); U26 : AO7 port map( A => n500, B => n503, C => n494, Z => O39_1_port); U27 : AO7 port map( A => n500, B => n504, C => n495, Z => O39_0_port); U28 : IV port map( A => clear, Z => n500); U29 : NR2 port map( A => clear, B => load, Z => n496); U30 : AN2 port map( A => load, B => n500, Z => n497); U31 : AO2 port map( A => temp_2_port, B => n496, C => data(0), D => n497, Z => n493); U32 : AO2 port map( A => temp_1_port, B => n496, C => data(1), D => n497, Z => n494); U33 : AO2 port map( A => temp_0_port, B => n496, C => data(2), D => n497, Z => n495); n498 <= '0'; n499 <= '0'; n501 <= '0'; end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity FSM is port( clk, rst : in std_logic; IR : in std_logic_vector (0 to 15); CC : in std_logic_vector (0 to 2); PC_ld : out std_logic; PC_mux : out std_logic_vector (0 to 1); IR_ld : out std_logic; MAR_mux : out std_logic_vector (0 to 1); MAR_gate : out std_logic; DR_addr : out std_logic_vector (0 to 2); DR_enable : out std_logic; SR1_addr, SR2_addr : out std_logic_vector (0 to 2); SR2_mux : out std_logic; ALU_sel : out std_logic_vector (0 to 1); CC_ld, MDR_ld, MAR_ld, PC_gate, ALU_gate, MDR_gate, MDR_mux, MIO_enable, Read_Write, PC_clear , MDR_clear, MAR_clear, IR_clear, CC_clear : out std_logic); end FSM; architecture SYN of FSM is component FJK2S port( J, K, CP, CD, TI, TE : in std_logic; Q, QN : out std_logic); end component; component FDS2L port( D, CP, CR, LD : in std_logic; Q, QN : out std_logic); end component; component AO7 port( A, B, C : in std_logic; Z : out std_logic); end component; component AO6 port( A, B, C : in std_logic; Z : out std_logic); end component; component AO4 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component AO3 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component ND3 port( A, B, C : in std_logic; Z : out std_logic); end component; component ND2 port( A, B : in std_logic; Z : out std_logic); end component; component OR2 port( A, B : in std_logic; Z : out std_logic); end component; component IV port( A : in std_logic; Z : out std_logic); end component; component NR2 port( A, B : in std_logic; Z : out std_logic); end component; component AO1 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component NR3 port( A, B, C : in std_logic; Z : out std_logic); end component; component AN3 port( A, B, C : in std_logic; Z : out std_logic); end component; component NR4 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component AO2 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component OR3 port( A, B, C : in std_logic; Z : out std_logic); end component; component EON1 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component ND4 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component AN2 port( A, B : in std_logic; Z : out std_logic); end component; component AN4 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component EO1 port( A, B, C, D : in std_logic; Z : out std_logic); end component; signal cpu_state_1_port, cpu_state_0_port, MAR_clear1208, execute_state954_2_port, TRAPVECTOR1338_2_port, DR1315_1_port, TRAPVECTOR_3_port, n1259, MAR_mux1365_1_port, TRAPVECTOR1338_6_port, n1289, SR1_addr1239_0_port, n1243_0_port, SR1_addr_0_port, DR_0_port, SR2_mux1349, TRAPVECTOR_7_port, cpu_state1017_0_port, DR_2_port, ALU_sel1354_1_port, PC_gate1218, SR1_addr_2_port, execute_state_1_port, TRAPVECTOR1338_4_port, SR1_addr1239_2_port, Read_Write1281, n1369_0_port, IR_ld1261, IR_clear1198, TRAPVECTOR_1_port, MDR_ld1266, n1279, TRAPVECTOR1338_0_port, PC_mux1291_1_port, ALU_gate1213, execute_state954_0_port, n1295_0_port, n1249_0_port, DR_enable1360, OPCODE1297_3_port, SR21309_1_port, DR_addr1233_2_port, OPCODE_2_port, MDR_clear1203, Imm, MAR_ld1256, SR2_addr1245_0_port, SR11303_0_port, link , n1363, OPCODE_0_port, n1216, n1231, n1211, n1264, SR11303_2_port, SR2_addr1245_2_port, DR_addr1233_0_port, OPCODE1297_1_port, SR21309_2_port, DR_addr1233_1_port, n1018_1_port, OPCODE1297_0_port, MDR_gate1228, PC_clear1193, n1226, PC_ld1276, n1274, OPCODE_3_port, OPCODE_1_port, SR2_addr1245_1_port, SR11303_1_port, n1254, n1221, n955_2_port, Imm1321, OPCODE1297_2_port, SR21309_0_port, n1284, DR1315_2_port, n1237_0_port, n1269, n1358_0_port, PC_mux1291_0_port, TRAPVECTOR1338_1_port, execute_state954_1_port, MDR_mux1286, CC_ld1271, TRAPVECTOR_4_port, MAR_gate1223, cpu_state1017_1_port, link1344, ALU_sel1354_0_port, n1347, execute_state_2_port, execute_state_0_port, MIO_enable_port, TRAPVECTOR1338_5_port, SR1_addr1239_1_port, TRAPVECTOR1338_7_port, SR1_addr_1_port, MIO_enable1251, DR_1_port, TRAPVECTOR_6_port, TRAPVECTOR1338_3_port, n1352, DR1315_0_port, MAR_mux1365_0_port, n2813, n2814, n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901, n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941, n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951, n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991, n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001, n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011, n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021, n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031, n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041, n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050, n3051, n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062, n3063, n3064, n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082, n3083, n3084, n3085, n3086, n3087, n3088, n3089, n3090, n3091, n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100, n3101, n3102, n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110, n3111, n3112, n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122, n3123, n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131, n3132, n3133, n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142, n3143, n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153, n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163, n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173, n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183, n3184, n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192, n3193, n3194, n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202, n3203, n3204, n3205, n3206, n3207, n3208, n3209, n3210 : std_logic; begin SR1_addr <= ( SR1_addr_2_port, SR1_addr_1_port, SR1_addr_0_port ); MIO_enable <= MIO_enable_port; cpu_state_reg_1_label : FJK2S port map( J => n3121, K => n3121, CP => clk, CD => n3124, TI => cpu_state1017_1_port, TE => n1018_1_port, Q => cpu_state_1_port, QN => open); DR_addr_reg_2_label : FDS2L port map( D => DR_addr1233_2_port, CP => clk, CR => n3126, LD => n1237_0_port, Q => DR_addr(0), QN => n3127); DR_addr_reg_1_label : FDS2L port map( D => DR_addr1233_1_port, CP => clk, CR => n3128, LD => n1237_0_port, Q => DR_addr(1), QN => n3129); DR_addr_reg_0_label : FDS2L port map( D => DR_addr1233_0_port, CP => clk, CR => n3130, LD => n1237_0_port, Q => DR_addr(2), QN => n3131); SR1_addr_reg_2_label : FDS2L port map( D => SR1_addr1239_2_port, CP => clk, CR => n3132, LD => n1243_0_port, Q => SR1_addr_2_port, QN => open); SR1_addr_reg_1_label : FDS2L port map( D => SR1_addr1239_1_port, CP => clk, CR => n3133, LD => n1243_0_port, Q => SR1_addr_1_port, QN => open); SR1_addr_reg_0_label : FDS2L port map( D => SR1_addr1239_0_port, CP => clk, CR => n3134, LD => n1243_0_port, Q => SR1_addr_0_port, QN => open); SR2_addr_reg_2_label : FDS2L port map( D => SR2_addr1245_2_port, CP => clk, CR => n3135, LD => n1249_0_port, Q => SR2_addr(0), QN => n3136); SR2_addr_reg_1_label : FDS2L port map( D => SR2_addr1245_1_port, CP => clk, CR => n3137, LD => n1249_0_port, Q => SR2_addr(1), QN => n3138); SR2_addr_reg_0_label : FDS2L port map( D => SR2_addr1245_0_port, CP => clk, CR => n3139, LD => n1249_0_port, Q => SR2_addr(2), QN => n3140); PC_mux_reg_1_label : FDS2L port map( D => PC_mux1291_1_port, CP => clk, CR => n3141, LD => n1295_0_port, Q => PC_mux(0), QN => n3142); PC_mux_reg_0_label : FDS2L port map( D => PC_mux1291_0_port, CP => clk, CR => n3143, LD => n1295_0_port, Q => PC_mux(1), QN => n3144); DR_reg_2_label : FDS2L port map( D => DR1315_2_port, CP => clk, CR => n3155, LD => n1347, Q => DR_2_port, QN => open); DR_reg_1_label : FDS2L port map( D => DR1315_1_port, CP => clk, CR => n3156, LD => n1347, Q => DR_1_port, QN => open); DR_reg_0_label : FDS2L port map( D => DR1315_0_port, CP => clk, CR => n3157, LD => n1347, Q => DR_0_port, QN => open); TRAPVECTOR_reg_7_label : FDS2L port map( D => TRAPVECTOR1338_7_port, CP => clk, CR => n3158, LD => n1347, Q => TRAPVECTOR_7_port, QN => open); TRAPVECTOR_reg_6_label : FDS2L port map( D => TRAPVECTOR1338_6_port, CP => clk, CR => n3159, LD => n1347, Q => TRAPVECTOR_6_port, QN => open); TRAPVECTOR_reg_4_label : FDS2L port map( D => TRAPVECTOR1338_4_port, CP => clk, CR => n3161, LD => n1347, Q => TRAPVECTOR_4_port, QN => open); TRAPVECTOR_reg_3_label : FDS2L port map( D => TRAPVECTOR1338_3_port, CP => clk, CR => n3162, LD => n1347, Q => TRAPVECTOR_3_port, QN => open); TRAPVECTOR_reg_1_label : FDS2L port map( D => TRAPVECTOR1338_1_port, CP => clk, CR => n3164, LD => n1347, Q => TRAPVECTOR_1_port, QN => open); ALU_sel_reg_1_label : FDS2L port map( D => ALU_sel1354_1_port, CP => clk, CR => n3166, LD => n1358_0_port, Q => ALU_sel(0), QN => n3167); ALU_sel_reg_0_label : FDS2L port map( D => ALU_sel1354_0_port, CP => clk, CR => n3168, LD => n1358_0_port, Q => ALU_sel(1), QN => n3169); MAR_mux_reg_1_label : FDS2L port map( D => MAR_mux1365_1_port, CP => clk, CR => n3170, LD => n1369_0_port, Q => MAR_mux(0), QN => n3171); MAR_mux_reg_0_label : FDS2L port map( D => MAR_mux1365_0_port, CP => clk, CR => n3172, LD => n1369_0_port, Q => MAR_mux(1), QN => n3173); Imm_reg : FDS2L port map( D => Imm1321, CP => clk, CR => n3174, LD => n1347, Q => Imm, QN => open); MAR_ld_reg : FDS2L port map( D => MAR_ld1256, CP => clk, CR => n3175, LD => n1259, Q => MAR_ld, QN => n3176); PC_clear_reg : FDS2L port map( D => PC_clear1193, CP => clk, CR => n3177, LD => n1211, Q => PC_clear, QN => n3178); MDR_clear_reg : FDS2L port map( D => MDR_clear1203, CP => clk, CR => n3179, LD => n1211, Q => MDR_clear, QN => n3180); MDR_gate_reg : FDS2L port map( D => MDR_gate1228, CP => clk, CR => n3181, LD => n1231, Q => MDR_gate, QN => n3182); PC_gate_reg : FDS2L port map( D => PC_gate1218, CP => clk, CR => n3183, LD => n1221, Q => PC_gate, QN => n3184); Read_Write_reg : FDS2L port map( D => Read_Write1281, CP => clk, CR => n3185 , LD => n1284, Q => Read_Write, QN => n3186); IR_clear_reg : FDS2L port map( D => IR_clear1198, CP => clk, CR => n3187, LD => n1211, Q => IR_clear, QN => n3188); MDR_mux_reg : FDS2L port map( D => MDR_mux1286, CP => clk, CR => n3189, LD => n1289, Q => MDR_mux, QN => n3190); MAR_clear_reg : FDS2L port map( D => MAR_clear1208, CP => clk, CR => n3192, LD => n1211, Q => MAR_clear, QN => n3193); IR_ld_reg : FDS2L port map( D => IR_ld1261, CP => clk, CR => n3194, LD => n1264, Q => IR_ld, QN => n3195); MIO_enable_reg : FDS2L port map( D => MIO_enable1251, CP => clk, CR => n3196 , LD => n1254, Q => MIO_enable_port, QN => open); MAR_gate_reg : FDS2L port map( D => MAR_gate1223, CP => clk, CR => n3197, LD => n1226, Q => MAR_gate, QN => n3198); CC_ld_reg : FDS2L port map( D => CC_ld1271, CP => clk, CR => n3199, LD => n1274, Q => CC_ld, QN => n3200); DR_enable_reg : FDS2L port map( D => DR_enable1360, CP => clk, CR => n3201, LD => n1363, Q => DR_enable, QN => n3202); MDR_ld_reg : FDS2L port map( D => MDR_ld1266, CP => clk, CR => n3203, LD => n1269, Q => MDR_ld, QN => n3204); ALU_gate_reg : FDS2L port map( D => ALU_gate1213, CP => clk, CR => n3205, LD => n1216, Q => ALU_gate, QN => n3206); PC_ld_reg : FDS2L port map( D => PC_ld1276, CP => clk, CR => n3207, LD => n1279, Q => PC_ld, QN => n3208); SR2_mux_reg : FDS2L port map( D => SR2_mux1349, CP => clk, CR => n3209, LD => n1352, Q => SR2_mux, QN => n3210); OPCODE_reg_1_label : FDS2L port map( D => OPCODE1297_1_port, CP => clk, CR => n3147, LD => n1347, Q => OPCODE_1_port, QN => n2813); cpu_state_reg_0_label : FJK2S port map( J => n3120, K => n3120, CP => clk, CD => n3124, TI => cpu_state1017_0_port, TE => n1018_1_port, Q => cpu_state_0_port, QN => n2814); OPCODE_reg_3_label : FDS2L port map( D => OPCODE1297_3_port, CP => clk, CR => n3145, LD => n1347, Q => OPCODE_3_port, QN => n2815); execute_state_reg_2_label : FJK2S port map( J => n3125, K => n3125, CP => clk, CD => n3124, TI => execute_state954_2_port, TE => n955_2_port, Q => execute_state_2_port, QN => n2816); execute_state_reg_1_label : FJK2S port map( J => n3123, K => n3123, CP => clk, CD => n3124, TI => execute_state954_1_port, TE => n955_2_port, Q => execute_state_1_port, QN => n2817); OPCODE_reg_0_label : FDS2L port map( D => OPCODE1297_0_port, CP => clk, CR => n3148, LD => n1347, Q => OPCODE_0_port, QN =>