--*************************************************************
--* This file is automatically generated test bench template  *
--* By ACTIVE-VHDL    <TBgen v1.10>. Copyright (C) ALDEC Inc. *
--*                                                           *
--* This file was generated on:            7:11 PM, 6/20/2002 *
--* Tested entity name:                               LC2_all *
--* File name contains tested entity:    $DSN\src\LC2_all.vhd *
--*************************************************************

library ieee;
use ieee.std_logic_arith.all;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;

   -- Add your library and packages declaration here ...

entity lc2_all_tb is
end lc2_all_tb;

architecture TB_ARCHITECTURE of lc2_all_tb is
   -- Component declaration of the tested unit
   component LC2_all
   port(
      rst : in std_logic;
      clk : in std_logic );
end component;

   -- Stimulus signals - signals mapped to the input and inout ports of tested entity
   signal rst : std_logic;
   signal clk : std_logic;
   -- Observed signals - signals mapped to the output ports of tested entity

begin

   -- Unit Under Test port map
   UUT : LC2_all
      port map
         (rst => rst,
         clk => clk );

process
   begin
   clk<='0';
   wait for 1 ns;
   clk<='1';
   wait for 1 ns;
end process;

process
begin
   rst <= '0';
   wait for 10 ns;
end process;

end TB_ARCHITECTURE;

configuration TESTBENCH_FOR_LC2_all of lc2_all_tb is
   for TB_ARCHITECTURE
      for UUT : LC2_all
         use entity work.LC2_all(str);
      end for;
   end for;
end TESTBENCH_FOR_LC2_all;