//Include the "Model" File and the "Testbench" File
#include "add1.cpp"
#include "add4_tst.cpp"
#include "vector.cpp"

int sc_main(int argc, char* argv[])
{
	//Declare signals to be tied to the modules
	sc_signal<sc_lv<4> > A_s,B_s,SUM_s;
	sc_signal<sc_logic> A3,A2,A1,A0,B3,B2,B1,B0,S3,S2,S1,S0;
	sc_signal<sc_logic> CIN_s,cout1,cout2,cout3,COUT_s;

	
	//Break Down a signal Input Vector into individual signal bits
	//Current SystemC version does not allow direct bit manipulation
	//of signals.
	vectorIn vector2bits1("Vector_2_BITS1");
	vector2bits1 << A_s << A3 << A2 << A1 << A0;

	vectorIn vector2bits2("Vector_2_BITS2");
	vector2bits2 << B_s << B3 << B2 << B1 << B0;

	//Instantiate 4 BIT_ADDERs to make a 4-bit ADDER
	BIT_ADDER adder1("BitAdder1");
	adder1 << A0 << B0 << CIN_s << S0 << cout1;

	BIT_ADDER adder2("BitAdder2");
	adder2 << A1 << B1 << cout1 << S1 << cout2;

	BIT_ADDER adder3("BitAdder3");
	adder3 << A2 << B2 << cout2 << S2 << cout3;

	BIT_ADDER adder4("BitAdder4");
	adder4 << A3 << B3 << cout3 << S3  << COUT_s;

	//Takes Signal Bits and combines them into a vector
	vectorOut bits2vector("bits2vector");
	bits2vector << S3 << S2 << S1 << S0 << SUM_s;

	//Instantiate a Testbench named "test1"
	testbench test1("TestBench1");
	test1  << A_s << B_s << CIN_s << SUM_s << COUT_s;

	//Run the Simulation for "200 nanosecnds"
	sc_start(200,SC_NS);

	return(0);
}