//Include the "Model" File and the "Testbench" File
#include "add1.cpp"
#include "add1_tst.cpp"

int sc_main(int argc, char* argv[])
{
	//Declare signals to be tied to the modules
	sc_signal<sc_logic> A_s,B_s,CIN_s,SUM_s,COUT_s;

	//Instantiate a BIT_ADDER named "adder1"
	//Note below the instantiation, one must associate
	//the inputs and outputs of a port in exact order.
	BIT_ADDER adder1("BitAdder1");
	adder1 << A_s << B_s << CIN_s << SUM_s << COUT_s;

	//Instantiate a Testbench named "test1"
	testbench test1("TestBench1");
	test1  << A_s << B_s << CIN_s << SUM_s << COUT_s;

	//Run the Simulation for "200 nanosecnds"
	sc_start(200,SC_NS);

	return(0);
}