Verilog for Digital Design Errata and Clarifications -------------------------- Although we exerted tremendous effort to ensure this first edition book would not contain with errors, a few errors may still manage to slip by. Below are mistakes found. Many thanks to the students and teachers who found them. Report errors to vahid@cs.ucr.edu and rlysecky@ece.arizona.edu. * Fig 5.24: The comparison should be "I_reg = 256" rather than "I_reg = 255". Fig 5.31: The above error in the comparison is also carried over into Figure 5.31 (Thanks to Nader Bagherzadeh of UC Irvine for detecting this error. 5/08).