Digital Design with RTL, VHDL, and Verilog 2nd edition Errata and Clarifications ------------------------- Although we exerted tremendous effort to ensure the book would not contain errors, a few errors may still manage to slip by. Below are mistakes found. Many thanks to the students and teachers who found them. Report errors to vahid@cs.ucr.edu. --------- Chapter 2 * Pg 45, Ex 2.1, number 3: Problem statement should be "Both a and b are 0" Currently says "not 0". (Thanks to Prof. Alper Sen, Bogazici University, Turkey, 3/8/13) * Pg 61: "(a + b + c)' = (abc)'" should be "(a + b + c)' = a'b'c'" (Thanks to Prof. Mahamed G.H. Omran, Gulf Univ of Science and Tech, 3/3/11) --------- Chapter 3 * Figure 3.47: Input is b, output is x (declarations are reversed). 2/24/11 * Figure 3.80: The value of "u" should be the inverse of "D". The error does not affect the main point of the diagram. (Thanks to Aswin Krishna, M.S. graduate student at Case Western, 3/25/10). EXERCISES * Exercise 3.23: Do not assign this exercise. It refers to a figure from the book's first edition, and thus the exercise description no longer matches the figure. (3/25/10) * Exercise 3.52: The delay of an XOR gate should have been included in the exercise description. Assume it is the same as for an AND gate. (3/25/10) --------- Chapter 4 * Pg 212, first full paragraph: -6 divided by 2 if done correctly should be -3, or 1101, not -1 as currently appears. Likewise, -6 multiplied by two should be -12, not -4 as currently appears. The point of the paragraph is still correct: normal shifts do not work for multiplying/dividing signed numbers by powers of 2. (Thanks to Prof. Mahamed Omran, Gulf Univ, Kuwait, 12/5/10) * Pg 214: "the maximum data value could be 18,137, which would require 15 bits" -- the max value is actually 26,010 (which would still require 15 bits). (Thanks to Felix Dujmenovic, 2/25/11) * Pg 220, Fig 4.72: the (a) and (b) are swapped. (Thanks to Jiang Hu, Texas A&M, 7/6/11). Chapter 4 slides: * Slide 9, in the wave diagram for 'D': there is one extra '0' in the middle for R1, R3, R5 and R7, (Thanks to Jiang Hu, Texas A&M, 7/6/11). * Slide 26, 2nd to last equation for 's': the prime is with the wrong parenthesis. (Thanks to Jiang Hu, Texas A&M, 7/6/11). --------- Chapter 5 * Figure 5.3: The transition from Wait to Disp should have its second term complemented, i.e.: c'*(tot