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FRANK N. VAHID

Professor, Department of Computer Science and Engineering
University of California, Riverside
(951) 827-4710, fax: (951) 827-4643, vahid@cs.ucr.edu, http://www.cs.ucr.edu/~vahid

RESEARCH INTERESTS

Embedded systems hardware/software design and applications. College CS / STEM education.

EDUCATION

• Ph.D. 1994, Information and Computer Science, University of California, Irvine
  Thesis title: Functional Partioning in System Design
  Advisor: Professor Daniel D. Gajski
  
• M.S. 1990, Information and Computer Science, University of California, Irvine
  Title: System Specification and Synthesis with the SpecCharts Language
  Advisor: Professor Daniel D. Gajski, GPA: 3.97/4.0
  
• B.S. (Highest Honors), 1988, Electrical and Computer Engineering, University of Illinois, Urbana
  Concentration: Computer Systems Design, GPA: 4.98/5.0
  

RESEARCH, EDUCATION AND INDUSTRY EXPERIENCE

• Professor 2003-present, Associate Professor 1999-2003, Assistant Professor 1994-1999, Department of Computer Science and Engineering, University of California, Riverside. Researched embedded system specification and design. Taught over 60 courses with a total of over 2000 students, with courses including - graduate: hardware/software engineering seminars, synthesis; upper-division: embedded systems (created and taught), algorithms/data-structures, and digital systems; lower-division: programming, freshmen orientation course (created and taught).
• Co-founder of zyBooks, 2012. Acquired by John Wiley and Sons 2019. Currently (2019-2022) serve as Chief Learning Officer. Creates web-native interactive animated learning material (textbook/homework replacements) and tools for CS and STEM topics.
• Consultant for various companies including Motorola (evaluated VHDL/Verilog IP development techniques), San Bernadino County Superintendent of Schools (developed Java-based educational software), NEC (developed system-level low power optimization techniques), Pulmonetics (analyzed software/hardware of a life-support ventilation system).
• Expert consultant 1999 to present, for 7 different embedded systems related patent infringement cases (deposed 3 times; testified in court 2 full days).
• Research Assistant / Lecturer 1988-1994 (Lecturer 1993), University of California, Irvine. Researched system-level synthesis, co-developing the Specify-Explore-Refine (SER) system-design methodology and the supporting SpecSyn system exploration tool. Developed a functional partitioning tool emphasizing constant-time incremental estimation. Developed the Program-State Machine (PSM) computation model and the supporting SpecCharts language as a VHDL front-end, which has evolved into the SpecC language and consortium (www.specc.org). Implemented a bit-sliced datapath layout generator. Lecturer for upper-division computer engineering course with 30 students. Teaching assistant for 1 upper- and 2 lower-division courses on computer organization.
• Engineer, Research and Development June 1989-Sept.1989, Hewlett-Packard, Santa Clara, CA. Developed a software interface to a VLSI design database currently in use by CAD tool developers.
• Engineer, Research and Development May 1987-Sept.1987, Applied Micro-Circuits Corporation, San Diego, CA. Developed logic compilers for use by design engineers.

PROFESSIONAL ACTIVITIES

• Senior member, IEEE.
• Member, ACM.
• Lead inventor on U.S. patent 7555658, "Embedded electronics building blocks for user-configurable monitor/control networks," May 10, 2005.
• Lead inventor on U.S. patent 7356672, "Warp processor for dynamic hardware/software partitioning," May 28, 2004.
• Co-inventor on a U.S. patent 6865526, "Method for core-based system-level power modeling using object-oriented techniques," June 24, 2000.
• Chair, UC Riverside Faculty of Engineering, 2008-2010.
• PC member / Senior PC member, ACM SIGCSE (Computer Science Education), 2016-2021.
• Steering committee member, program committee member, IEEE/ACM Int. Conference on Hardware/Software Codesign and System Synthesis (CODES/ISSS) and Embedded Systems Week (ESWEEK), 2003-2020. ESWEEK publications chair 2007-2009.
• Program committee member, IEEE/ACM Design Automation Conference (DAC), 2009, 2010, 2011 (topic chair)
• Program committee member, IEEE/ACM Design Automation and Test in Europe Conf. (DATE), 1995, 1996, 1998, 1999, 2003-2011.
• General Chair, 8th IEEE/ACM Int. Workshop on Hardware/Software Codesign (CODES), San Diego, USA.
• Program chair, 7th IEEE/ACM Int. Workshop on Hardware/Software Codesign (CODES), Italy, 1999.
• General chair, 10th IEEE/ACM Int. Symp. on System Synthesis (ISSS), Antwerp, Belgium, 1997.
• Program chair, 9th IEEE/ACM Int. Symp. on System Synthesis (ISSS), San Diego, USA, 1996.
• Program committee member, IEEE/ACM Int. Conf. on Computer Aided Design (ICCAD), 2000, 2001, 2002.
• Program committee member, IEEE/ACM CODES, 1996, 1997, 1998, 1999, 2000, 2001,
• Program committee member, ACM MICRO conference, 2003.
• Program committee member, IEEE/ACM ISSS, 1998, 1999, 2000, 2001.
• Program committee member, IEEE Int. Conf. on Field Programmable Logic and Applications (FPL), 2007.
• Program committee member, Compilers, Architectures and Synthesis for Embedded Systems (CASES), 2000, 2002, 2003, 2005.
• Program committee member, ACM SIGPLAN Conference and Languages, Compilers and Tools for Embedded Systems (LCTES), 2003.
• Guest Editor, Special Issue of ACM Trans. on Design Automation of Electronic Systems, Vol. 2, No. 4, Oct. 1997.

TUTORIALS and SELECTED INVITED PRESENTATIONS

• Invited talks at over 50 universities on CS / CE education, 2016-present, including: Texas A&M, Univ. of Illinois Urbana/Champaign, Univ. of Florida, Univ. of Texas (Austin), UT San Antonio, Florida International Univ., Florida Atlantic Univ., Miami Univ., Miami Dade Community College, Drexel, Tufts, Univ. of Massachusetts Lowell, The College of New Jersey, Southern New Hampshire Univ., Univ. of Minnesota Twin Cities, Univ. of Minnesota Duluth, Michigan State Univ. Central Michigan Univ., Indiana State Univ., California State Univ. Northridge, California State Univ. Fresno, San Jose State Univ., Univ. of New Mexico, New Mexico State Univ., Univ of Alabama Birmingham, Univ. of Alabama Tuscaloosa, Lone Star College, UT Rio Grande Valley, Boston Univ., Rutgers, New Jersey Institute of Technology, Jacksonville State Univ., Oklahoma State, Texas State, Iowa State, Univ. of Nebraska. Dozens of online talks and webinars as well to dozens of other schools and hundreds of faculty.
• Invited talk, embedded systems education and modern web-based learning, Complutense Univ (Madrid), 2014
• ASEE invited talk and panel, online learning, 2014
• Invited talk, animated interactive learning, SJSU NSF MOOCs workshop, 2014.
• Invited talk, digital mockups, Texas A&M, 2013.
• Invited talk, digital mockups, Univ of Arkansas, 2013.
• Invited talk, future of textbooks, UC Online Education workshop, Berkeley 2011.
• Invited talk, warp processing, UT Austin, 2009.
• Keynote talk, Reconfigurable Architectures Workshop (RAW), May 2009, Rome, Italy.
  
• Keynote talk, Workshop on Embedded Systems Education (WESE), Oct 2008, Atlanta, Georgia
  
• Invited speaker, National Science Foundation Cyber-Physical Workshop, July 2007
• System-Level Design panelist, Intel research symposium, 2005.
  
• Distinguished lecturer, Arizona State Univ., CSE Dept, 2004.
• IBM Research, Yorktown Heights, 2004.
  
• Keynote Talk, Embedded Systems Codesign conference, 2002.
  
• IEEE/ACM Design Automation Conference (DAC) full-day tutorial on New Computing Platforms for Embedded Systems, 2002.
  
• ASIC half-day tutorial on IP-based design, Rochester, 1998
  
• APCHDL half-day tutorial on codesign, Taiwan, 1997
  
• ED&TC half-day tutorial on codesign, France, 1997
  
• ICCAD full-day tutorial on codesign, San Jose, 1995
  
• EuroDAC full-day tutorial on codesign, England, 1995
  
• VLSI full-day tutorial on codesign, New Delhi, 1995
  
• EDAC full-day tutorial on codesign, France, 1994
  
• INPG two-day seminar on SpecSyn, France, 1994
  
  
• Xilinx, 2009.
• University of Texas, Austin, ECE Colloquium, 2009
• Xilinx, 2008.
• Microsoft Research, 2008.
• University of Washington, ECE Colloquium, 2008.
• University of California, San Diego, ECE Colloquium, 2008.
• University of Illinois, Urbana/Champaign, ECE Colloquium, 2008.
• University of California, Los Angeles, ECE Colloquium, January 2008.
• University of Arizona, Tucson, ECE Colloquium, 2006.
• University of California, San Diego, CSE Colloquium, April 2005.
• Distinguished Lecture, Arizona State University, ECE, Tempe, 2004.
• University of California, San Diego, ECE Colloquium, November 2002.
• Triscend Corp., Mountain View, CA, September 2002.
• Southern California Embedded Systems Symposium, Jazz Semiconductors, Newport Beach, CA, September 2002.
• Synplicity Inc., Sunnyvale, CA, March 2002.
• Triscend Corp., Mountain View, CA, March 2002.
• NEC C&C Research Labs, Princeton, NJ, March 2001.
• University of California, Riverside, CSE Colloquium, November 2000.
• University of California, Berkeley, CAD Seminar, February 2000.
• University of California, Los Angeles, CS Colloquium, 2000.
• NEC C&C Research Labs, Princeton, NJ, July 2000.
• University of California, Irvine, CECS Embedded Systems Seminar, March 1999.
• University of California, Irvine, ECE Colloquium, March 1999.

AWARDS AND HONORS

• Inducted to UCI's Computer Science Hall of Fame, 2020
• UCR's Innovative Teaching Award 2015-2016
• Best paper, ASEE 2015 (American Society of Engineering Educators Annual Conference).
• Best paper, ASEE 2014 (American Society of Engineering Educators Annual Conference).
• Best papers of ACM FPGA Symposium for 2012, invited for special follow-on journal issue in ACM Trans. on Reconfigurable Technology and Systems.
• Dissertation of the Year for 2006, awarded to Ph.D. student Roman Lysecky by the European Design Automation Association, in the category of Embedded Systems.
• Best Papers in Architecture recognition for CASES 2003 paper, recognized with paper in Special Issue of IEEE Transaction on Computers, 2005.
  
• Distinguished Teaching Award from the UCR College of Engineering, 2004.
  
• Best Paper Award Workshop on Compilers and Operating Systems for Low Power (COLP), 2001.
  
• Best Paper Award Design Automation and Test in Europe (DATE) conference, 2000.
  
• Best Paper Award IEEE Transactions on VLSI, 2000.
  
• NSF CAREER award, 1999-2003.
  
• Outstanding Teacher of the UCR College of Engineering, 1998.
  
• Regent's Faculty Fellow University of California, 1998 and 1996.
  
• Semiconductor Research Corporation (SRC) Graduate Fellow UC Irvine, 1990-1994.
  
• Chancellor's Fellow UC Irvine, 1988-1989.
  
• Bronze Tablet Top 3 percent of University of Illinois Engineering graduating class, 1988.
  
• Best Paper Nomination European Design Automation Conference, Sept. 1994.
  
• Best Paper Nomination Design Automation Conference, June 1992.
  

STUDENTS GRADUATED

Ph.D.

• Joe Allen, CS&E Ph.D. 2021.
• Bailey Miller, CS&E Ph.D. 2014. Was engineer at SpaceX, now Engineering Director at zyBooks.
• Alex Edgcomb, CS&E Ph.D. 2014. Developer at zyBooks.com.
• Chen Huang, CS&E Ph.D. 2012. Engineer at Amazon.
• David Sheldon, CS&E Ph.D. 2011. Engineer at Altera.
• Scott Sirowy, CS&E Ph.D. 2010.
• Ann Gordon-Ross, CS&E Ph.D. 2007. Associate Professor at the University of Florida, Gainesville (ECE). NSF CAREER Award recipient.
• Greg Stitt, CS&E Ph.D. 2007. Associate Professor at the University of Florida, Gainesville (ECE).
• Susan Lysecky (formerly Susan Cotterell), CS&E Ph.D. 2006. Was Assistant Professor at the University of Arizona (ECE).
• Roman Lysecky, CS&E M.S. 2000, Ph.D. 2005. Professor Emeritus at the University of Arizona (ECE), now VP Content at zyBooks. NSF CAREER Award recipient.
• Chuanjun Zhang, CS&E Ph.D. 2004. Was Assistant Professor at the University of Missouri, Kansas City(ECE), currently Intel Research / CMU.
• Tony Givargis, CS&E Ph.D. 2001. Currently Professor and CS Dept Chair at Univ. of California, Irvine, . ASEE 2011 Ternan award recipient.
• Enoch Hwang, CS&E Ph.D. 1998. Currently Professor at La Sierra Univ., Riverside, California.
• Joe Allen, Bailey Miller, David Sheldon, Scott Sirowy, Ann Gordon-Ross, Greg Stitt, Susan Lysecky, Roman Lysecky, and Tony Givargis each began working with me as undergraduate researchers.

M.S.

• Ford St. John (MS CS 2021)
• Shayan Salehian (MS CS 2018)
• Bailey Herms (MS CS 2018)
• Joshua Yuen (MS CS 2016)
• Tim Cherney (MS CS 2015)
• Alex Edgcomb (MS CS 2012)
• Bailey Miller (MS CS 2012)
• Yasaman Sameisy (MS CS 2010)
• Shawn Nemetebakshi(MS CS 2005)
• Kelly Downey (MS EE 2004) (Now a UCR lecturer)
• Brian Grattan (MS EE 2002)
• Weijun Zhang, EE M.S. 2001 (Silicon Valley).
• Deepa Varghese CS&E M.S. 1998 (Motorola).
• Linus Tauro, CS&E M.S. 1997 (Quick-Logic).
• Thuy Le, CS&E M.S. 1997 (IMA).
• William Kang, CS&E M.S. 1995 (TRW).
• Rosely Ng, CS&E M.S. 1995 (IMA).
• Joshua Yuen, Tim Cherney, Bailey Miller, Shawn Nemetebakshi, and Kelly Downey each began working with me as undergraduate researchers.

Present graduate students

• Joe Allen (Ph.D.)
• Nabeel Alzahrani (Ph.D.)
• Shayan Salesian (M.S.)
• Bailey Herms (M.S.)

B.S. (other students who actively participated in research in my lab as undergraduates)

• Kevin Nguyen (2016-current)
• Sirina Nabhan (2015-2017) (woman)
• Lorraine Diaz (2015-2016) (woman)
• John Dixon (2015-2016)
• Brittany Seto (2014-2015) (woman)
• Richard Stinnet (2014-2015)
• Nicholas Gingerella (2013-2014)
• Arash Nabili (2015 at UC Irvine, now at UCLA for Ph.D.)
• Sean Mumford, CS B.S. 2013, now at Western Digital
• Nathan Martin, CS B.S. 2012
• Francesca Perkins, CS B.S. 2012 (woman)
• Isabel Mendoza, CS B.S. 2012 (woman)
• Josephine Havers, CS B.S. 2012 (woman)
• Daphne Ferreiro, CS B.S. 2013 (woman)
• Andrew Becker, CS B.S. 2011 (now Ph.D. student at EPFL)
• Lauren Samy, CS B.S. 2011 (now Ph.D. student at UCLA) (woman)
• Louis Alex Eisner, CS B.S. 2010
• Andrea Coba, CE B.S. 2008, now at Western Digital (woman)
• Robert (Mike) Ballou, CE B.S. 2008
• Jonathon Basseri, CE B.S. 2008
• Margaret Ukwu, CE B.S. 2009 (woman)
• Casey Czechowski, CE B.S. 2007, completed M.S. at UCR (woman)
• Caleb Leak, CE B.S. 2007
• Josef Spjut, CE B.S. in 2006, now Ph.D. student at Utah
• Cathy Vu, CS B.S. in 2004, completed M.S. at UCR (woman)
• Korey Sewell, CS B.S. in 2004, (MSRIP program), went on as graduate student at U. Michigan
• San Nguyen, CS B.S. in 2004, (MSRIP program), completed M.S. at UCR.
• Ed Garcia, CS B.S. in 2004
• Daniel Tan, EE B.S. in 2004, went to Boeing
• Ron Feliciano, CS B.S. in 2004, obtained CS M.S. at UCR.
• Rafael Lopez, CS B.S. in 2002, (MSRIP program), Ph.D. student at UC Irvine
• Kris Miller, CS B.S. in 2001, currently UCR CS lecturer
• Puneet Mehra, CS B.S. in 1999, went to UC Berkeley for Ph.D.
• Shannon Alfaro, CS B.S. in 1999, M.S. from UC Irvine, now a lecturer at UC Irvine (woman)
• Jason Villarreal, CS B.S. in 1999 (Ph.D. 2009 UCR)
• Victor Hill, CS B.S. in 1999 (Now UCR system administrator)

FUNDING AND EQUIPMENT DONATIONS

• $500,000, National Science Foundation, "Teaching introductory CS: Shifting from detecting/punishing cheating to gaining programming behavior insight", 2021-2024.
• (Key author for four awarded NSF SBIR grants totalling about $3,000,000 to date).
• $1,000,000, National Science Foundation, "CSR: Medium: modeling and synthesis for application-specific multicore systems-on-a-chip", PI (with co-PI's Roman Lysecky at Univ. of Arizona, Tony Givargis at UC Irvine), 2016 - 2021
• $250,000, National Science Foundation, "MATH:EAGER: Improving Algebra Learning via Real-Life Applications and Games", PI, Jul 2015 - Jun 2017.
• $61,500, Google Faculty Research Award, "“Why Interactive Online Learning Material Works”, PI, Feb 2015.
• $1,500,000, National Science Foundation, "Design Science for CPS," co-PI, joint with D. Gajski (PI) and T. Givargis (co-PI) at UC Irvine, Oct 2011 - Sep 2015. (UCR share: $350,000). Plus several REU's added to grant.
• $40,000 (gift), Semiconductor Research Corporation, "ASICs for Biomedical Applications," PI, Mar 2011 - Feb 2012.
• $500,000, National Science Foundation, "CSR: Synthesis of Time-Controllable Digital Mockups of Physical Systems," PI, joint with Tony Givargis at UC Irvine, July 2010 - June 2013. (UCR share: $300,000).
• $18,000, National Science Foundation, REU supplement to above award, July 2011 - June 2012.
• $30,000, UCOP Online Instruction Pilot Project, "Programming Embedded Systems," PI.
• $800,000, U.S. Dept. of Education GAANN Award (Graduate Assistance in Areas of National Need), co-PI, joint with V. Tsotras (PI), E. Keogh (co-PI), W. Najjar (co-PI), June 2009 - May 2013.
• $150,000, National Science Foundation, "DUE: Collaborative Research: Integrating Time-Oriented Embedded System Programming into a Computing Curriculum," PI, joint with Tony Givargis at UC Irvine, June 2009 - May 2011.
• $24,000, National Science Foundation, "CSR EHS: Standard Binaries for FPGAs: Separating Function and Architecture in Modern Embedded Computing Platforms ," PI, travel funds for cooperation project with Brazilian universities.
• $2,500,000, Office of Naval Research, Collaborator with 11 UCR engineering faculty on "Aware Building" project, July 2007 - June 2010.
• $320,000, National Science Foundation, "CSR EHS: Standard Binaries for FPGAs: Separating Function and Architecture in Modern Embedded Computing Platforms ," July 2006 - Jun 2011.
• $180,000, Semiconductor Research Corporation, "Warp Processing," July 2005 to Jun 2008.
• $360,000, National Science Foundation, "eBlocks: Embedded System Building Blocks," August 2003 - July 2008.
• $70,000, National Science Foundation, Broadening Participation in Computing (BPC) supplement to "eBlocks: Embedded System Building Blocks," August 2005 - July 2007.
• $180,000, National Science Foundation, "Collaborative Research: Platform-Oriented CAD for Power and Performance Optimization," August 2002 - July 2006, with Prof. Nik Dutt at UC Irvine.
• $400,000, National Science Foundation, "Computer Science, Engineering, and Mathematics Scholarships Program" September 1, 2002 - August 31, 2006, co-PI with Prof. Keith Oddson and Prof. Mark Matsumoto.
• $7,500, National Science Foundation, Research Experience for Undergraduates, July 2002 - June 2003.
• $20,000, TriMedia Corporation, "Optimizing system-on-a-chip memory architectures for video/audio processing applications," March 2001.
• $15,000, DiMI match to TriMedia grant, March 2001.
• $10,000, National Science Foundation, Research Experience for Undergraduates, July 2000 to June 2001.
• $10,000, NEC C&C Research Labs, January 2000.
• $7,875, UC MICRO match of NEC donation, January 2000.
• $214,000, National Science Foundation, "Core IP Support in System Specifications for System-Level Interface Optimization," July 1998 - June 2001.
• $260,000 National Science Foundation, "IP-Based Embedded Systems Design," CAREER proposal, July 1999 - June 2003.
• 20,000, National Science Foundation, "Research Experience for Undergraduates Supplement to NSF Award," July 1998 - June 2001.
• $24,000, Design Automation Conference Graduate Scholarship, "Interface exploration for core-based systems," July 1998 - June 2000.
• $10,000, Avanti Corporation, "Power Consumption in Functionally- Partitioned Systems," July 1997 - June 1998. UC MICRO match of $4,439.
• $3,656, UC Micro, "Embedded System Communiation Libraries and Synthesis," July 1997 - June 1998.
• $3,100, and $5,000, UCR Regent's Faculty Fellowship, 1998 and 1996 respectively.
• $5,000, Harmon Industries, "Embedded system design for safety techniques," July 1997.
• $12,000, Design Automation Conference Graduate Scholarship, "Hardware/software partitioning and communication," July 1996 - June 1997.
• Miscellaneous UCR Academic Senate grants.

• $5,000 Xilinx donations of FPGA development boards
• $10,000 Intel donation of 4 PCs for research
• $25,000 Xilinx donation of various FPGA development boards
• $50,000 IBM donation of Chameleon Blade (Cell processor plus FPGA platform)
• $19,900, Triscend Corporations, 20 development kits for the E5 single-chip microprocessor/FPGA device, 2002.
• $1,500, Trimedia Corp., development software kit and hardware board for the Trimedia processor, 2001.
• $180,000, Xilinx, 20 stations of Xilinx Foundation Express software and XESS FPGA/CPLD/8051 development hardware, 2000.
• $20,000, Windriver VxWorks and Tornado software for real time systems development, 1999.
• $360,000, Xilinx, 40 stations of Xilinx Foundation Express software and XESS FPGA/CPLD/8051 development hardware, 1998-1999.
• $5,000, Intel, 5 Pentium-based embedded processor development boards and software, 1998.
• $17,020, Phillips Semiconductors, 8 8051 development stations (emulators, programmers, microcontrollers), 1997.
• $5,400, Motorola, 12 Coldfire 32-bit embedded processor development boards, 1997.
• $120,000, Keil Software, 80 8051 C-compiler and debugger software licenses, 1996.

PUBLICATIONS

Books

zyBooks on C++, C, Java, Digital Design, others. (2013 - 2018) Used by 500 universities, 100,000 students, 1,000 instructors.

Programming Embedded Systems: An Introduction to Time-Oriented Programming   By Frank Vahid, Tony Givargis, and Bailey Miller, zyBooks.com, 2011.

Digital Design, with RTL, VHDL, and Verilog   By Frank Vahid, John Wiley and Sons publishers, 2nd edition, 2011. Adopted by several dozen universities worldwide so far, including several top-20 universities.

VHDL for Digital Design   By Frank Vahid and Roman Lysecky, John Wiley and Sons publishers, 2007.
Verilog for Digital Design   By Frank Vahid and Roman Lysecky, John Wiley and Sons publishers, 2007.

Embedded System Design -- A Unified Hardware/Software Introduction   By Frank Vahid and Tony Givargis, published by J. Wiley and Sons, ) 2002.

Specification and Design of Embedded Systems   By Dan Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong, published by Prentice Hall, 1994. Perhaps the first book on embedded systems.

Journal and Conference Papers (excerpted from http://www.cs.ucr.edu/~vahid/pubs)

J. Yuen, A. Edgcomb, and F. Vahid. Will Students Earnestly Attempt Learning Questions if Answers are Viewable?, Proceedings of ASEE Annual Conference, 2016.

A. Edgcomb and F. Vahid. Simplifying a Course to Reduce Student Stress so Students Can Focus Again on Learning, Proceedings of ASEE Annual Conference, 2016.

F. Vahid, S. Lysecky, and A. Edgcomb. Introduction to Computing Technology: New Interactive Animated Web-Based Learning Content, Proceedings of ASEE Annual Conference, 2016.

F. Vahid, A. Edgcomb, S. Lysecky, and R. Lysecky. New Web-Based Interactive Learning Material for Digital Design, Proceedings of ASEE Annual Conference, 2016.

F. Vahid, A. Edgcomb, B. Miller, and T. Givargis. Learning Materials for Introductory Embedded Systems Programming using a Model-Based Discipline, Proceedings of ASEE Annual Conference, 2016.

F. Vahid and A. Edgcomb. New College-Level Interactive STEM Learning Material: Findings and Directions, AAAS NSF Symposium on EnFUSE (Envisioning the Future of Undergraduate STEM Education: Research and Practice), 2016.

F. Vahid, D. de Haas, S. Strawn, A. Edgcomb, S. Lysecky, R. Lysecky. A Continual Improvement Paradigm for Modern Online Textbooks. Int. Conf. of Education, Research and Innovation (ICERI), Spain, Nov. 2015.

A. Edgcomb, D. De Haas, R. Lysecky, F. Vahid. Student usage and behavioral patterns with online interactive textbook materials. Int. Conf. of Education, Research and Innovation (ICERI), Spain, Nov. 2015.

A. Edgcomb, F. Vahid. How Many Points Should Be Awarded for Interactive Textbook Reading Assignments? Proc. of Frontiers in Education conference (FIE), El Paso, Oct. 2015.

A. Edgcomb, F. Vahid, R. Lysecky, Students Learn More with Less Text that Covers the Same Core Topics Proc. of Frontiers in Education conference (FIE), El Paso, Oct. 2015.

A. Edgcomb, F. Vahid. Effectiveness of Online Textbooks vs. Interactive Web-Native Content American Society of Engineering Educators Annual Conference, ASEE 2014, Received best paper award.

A. Edgcomb, F. Vahid. Accurate and Efficient Algorithms that Adapt to Privacy-Enhanced Video for Improved Assistive Monitoring ACM Transactions on Management Information Systems (TMIS): Special Issue on Informatics for Smart Health and Wellbeing, 2013.

B. Miller, F. Vahid, T. Givargis, P. Brisk. Graph-Based Approaches to Placement of Processing Element Networks on FPGAs for Physical Model Simulation. ACM Transactions on Reconfigurable Technology and Systems. 2014.

B. Miller, F. Vahid, T. Givargis. Exploration with upgradeable models using statistical methods for physical model emulation IEEE/ACM Design Automation Conference (DAC'13), June 2013.

S. Peter, F. Vahid, T. Givargis. A Ball Goes to School – Our Experiences from a CPS Design Experiment. Workshop on Cyber-Physical Systems Education (CPS-Ed) at Cyber Physical Systems Week (CPSWeek), pp. 1-4, Philadelphia, April 2013.

B. Miller, F. Vahid, T. Givargis. Embedding-based placement of processing element networks on FPGAs for physical model simulation. ACM Int. Symp. on FPGAs, Feb 2013, pp 181-190.

C. Huang, B. Miller, F. Vahid, T. Givargis. Synthesis of networks of custom processing elements for real-time physical system emulation. ACM Trans. on Design Automation of Electronic Systems (TODAES), Vol 18, Issue 2, April 2013, 21 pages.

A. Edgcomb, F. Vahid. Automated In-Home Assistive Monitoring with Privacy-Enhanced Video. IEEE International Conference on Healthcare Informatics (ICHI), 2013.

A. Edgcomb, F. Vahid. Estimating Daily Energy Expenditure from Video for Assistive Monitoring. IEEE International Conference on Healthcare Informatics (ICHI), 2013.

A. Edgcomb, F. Vahid. Interactive Web Activities for Online STEM Learning Materials. American Society for Engineering Education Pacific Southwest Section Conference, 2013.

T.S. Chou, C. Huang, B. Miller, T. Givargis, F. Vahid. An Efficient Compression Scheme for Checkpointing of FPGA-Based Digital Mockups. IEEE/ACM Asian and South Pacific Design Automation Conference (ASP-DAC), Japan, January 2013.

A. Edgcomb, F. Vahid. Privacy Perception and Fall Detection Accuracy for In- Home Video Assistive Monitoring with Privacy Enhancements. ACM SIGHIT (Special Interest Group on Health Informatics) Record, 2012.

C. Huang, B. Miller, F. Vahid, T. Givargis. Synthesis of Custom Networks of Heterogeneous Processing Elements for Complex Physical System Emulation. IEEE/ACM Conference on Hardware/Software Codesign and System Synthesis (CODES/ISSS, part of ESWEEK), Finland, Oct 2012

B. Miller, F. Vahid, T. Givargis. RIOS: A Lightweight Task Scheduler for Embedded Systems. Workshop on Embedded Systems Education (WESE, part of ESWEEK), Finland, Oct 2012

A. Edgcomb, F. Vahid. Automated Fall Detection on Privacy-Enhanced Video. Engineering in Medicine and Biology Conference (EMBC), San Diego, August 2012.

B. Miller, F. Vahid, T. Givargis. MEDS: Mockup Electronic Data Sheets for Automated Testing of Cyber-Physical Systems Using Digital Mockups. Design Automation and Test in Europe, March 2012

B. Miller, F. Vahid, T. Givargis. Digital Mockups for the Testing of a Medical Ventilator, ACM SIGHIT Symposium on International Health Informatics (IHI), 2012, pp. 859-862.

A. Edgcomb, F. Vahid. MNFL: The Monitoring and Notification Flow Language for Assistive Monitoring, ACM SIGHIT International Health Informatics Symposium (IHI), 2012, pp. 191-200.

C. Huang, F. Vahid, and T. Givargis. A Custom FPGA Processor for Physical Model Ordinary Differential Equation Solving, IEEE Embedded Systems Letters, September 2011, pp. 113-116.

A. Edgcomb, F. Vahid. Feature Extractors: Flexible Integration of Cameras and Sensors for End-User Programming of Assistive Monitoring Systems, Wireless Health, 2011, 2 pages.

G. Stitt and F. Vahid. Thread Warping: Dynamic and Transparent Synthesis of Thread Accelerators. ACM Trans. on Design Automation of Electronic Systems (TODAES), Vol 16, Issue 3, June 2011, 21 pages.

A. Becker, S. Sirowy, F. Vahid. Just-in-Time Compilation for FPGA Processor Cores. IEEE Electronic System Level Synthesis Conf. (ESLsyn), June 2011.

B. Miller, T. Givargis, F. Vahid. Application-Specific Codesign Platform Generation for Digital Mockups in Cyber-Physical Systems. IEEE Electronic System Level Synthesis Conf. (ESLsyn), June 2011.

C. Huang, F. Vahid. Scalable Object Detection Accelerators on FPGAs Using Custom Design Space Exploration. IEEE Symposium on Application Specific Processors (SASP), June 2011.

S. Sirowy, C. Huang, and F. Vahid. Online SystemC Emulation Acceleration. IEEE/ACM Design Automation Conference, June 2010.

C. Huang and F. Vahid. Server-Side Coprocessor Updating for Mobile Devices with FPGAs. ACM Int. Symp. on FPGAs, Feb 2010.

S. Sirowy, T. Givargis, F. Vahid. Digitally-Bypassed Transducers: Interfacing Digital Mockups to Real-Time Medical Equipment. Int. Conf. of the IEEE Engineering in Medicine and Biology Society (EMBC), Sept 2009.

S. Sirowy, C. Huang, and F. Vahid. Dynamic Acceleration Management for SystemC Emulation. Workhop on Adaptive and Reconfigurable Embedded Systems (APRES, part of ESWEEK), Oct 2009.

S. Sirowy, B. Miller, and F. Vahid. Portable SystemC-on-a-Chip. IEEE/ACM Conference on Hardware/Software Codesign and System Synthesis (CODES/ISSS, part of ESWEEK), Oct 2009.

C. Huang, F. Vahid. Dynamic Transmuting Coprocessors. IEEE/ACM Design Automation Conference, July 2009.

F. Vahid. What is Hardware/Software Partitioning? ACM SIGDA Newsletter, June 2009.

D. Sheldon, F. Vahid. Making Good Points: Application-Specific Pareto-Point Generation for Design Space Exploration using Statistical Methods. ACM Symp. on FPGAs, Feb 2009.

R. Lysecky, F. Vahid. Design and Implementation of a MicroBlaze-based Warp Processor. ACM Transactions on Embedded Computing Systems (TECS), April, 2009, 22 pages

S. Sirowy, D. Sheldon, T. Givargis, and F. Vahid. Virtual Microcontrollers ACM SIGBED Review, Vol. 6., Issue 1, 2009.

S. Lysecky and F. Vahid. Enabling Non-Expert Construction of Basic Sensor-Based Systems ACM Trans. on Computer-Human Interaction (TOCHI), 2009

A. Gordon-Ross, F. Vahid, and N. Dutt. Fast Configurable-Cache Tuning with a Unified Second-Level Cache . IEEE Transactions on VLSI, 2008.

S. Sirowy, D. Sheldon, T. Givargis, and F. Vahid. Virtual Microcontrollers. Int. Wkshp. on Embedded Systems Education, (WESE), Oct 2008.

F. Vahid and T. Givargis. Timing is Everything -- Embedded Systems Demand Teaching of Structured Time-Oriented Programming. Int. Wkshp. on Embedded Systems Education, (WESE), Oct 2008.

C. Huang, D. Sheldon, and F. Vahid. Dynamic Tuning of Configurable Architectures: The AWW Online Algorithm . IEEE/ACM Int. Conf. on Hardware/Software Codesign and System Synthesis, (CODES/ISSS), Oct 2008.

D. Sheldon and F. Vahid. Don't Forget Memories: A Case Study Redesigning a Pattern Counting ASIC Circuit for FPGAs. IEEE/ACM Int. Conf. on Hardware/Software Codesign and System Synthesis, (CODES/ISSS), Oct 2008.

F. Vahid and T. Givargis. Highly-Cited Ideas in System Codesign and Synthesis. IEEE/ACM Int. Conf. on Hardware/Software Codesign and System Synthesis, (CODES/ISSS), Oct 2008.

C. Huang and F. Vahid. Dynamic Coprocessor Management for FPGA-Enhanced Compute Platforms. IEEE/ACM Int. Conf. on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), Oct 2008.

F. Vahid, G. Stitt, and R. Lysecky. Warp Processing: Dynamic Translation of Binaries to FPGA Circuits . IEEE Computer, Vol. 41, No. 7, July 2008, pp. 40-46.

P. Viana, A. Gordon-Ross, E. Barros, F. Vahid. A Table-Based Method for Single-Pass Cache Optimization. ACM Great Lakes Symposium on VLSI, May 2008, pp. 71-76.

S. Sirowy, G. Stitt, and F. Vahid. C is for Circuits: Capturing FPGA Circuits as Sequential Code for Portability. ACM Int. Symp. on FPGAs, 2008.

F. Vahid and G. Stitt. Hardware/Software Partitioning . Chapter 26 in S. Hauck, A. DeHon (editors), Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation", Morgan Kaufmann/Elsevier, 2008.

F. Vahid. It's Time to Stop Calling Circuits Hardware. IEEE Computer Magazine, September 2007.

G. Stitt and F. Vahid. Thread Warping: A Framework for Dynamic Synthesis of Thread Accelerators. Int. Conf. on Hardware/Software Codesign and System Synthesis (CODES/ISSS), 2007, pp. 93-98.

A. Gordon-Ross and F. Vahid. A Self-Tuning Configurable Cache. Design Automation Conference (DAC), 2007.

K. Schleupen, S. Lekuch, R. Mannion, Z. Guo, W. Najjar, and F. Vahid. Dynamic Partial FPGA Reconfiguration in a Prototype Microprocessor System . (FPL), 2007.

G. Stitt and F. Vahid. Binary Synthesis. ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 12 No. 3, Aug 2007.

S. Sirowy and F. Vahid. Integrated Coupling and Clock Frequency Assignment. International Embedded Systems Symposium (IESS), 2007.

D. Sheldon, F. Vahid and S. Lonardi. Soft-Core Processor Customization Using the Design of Experiments Paradigm. IEEE/ACM Design Automation and Test in Europe (DATE), 2007, pp. 821-826.

A. Gordon-Ross, P. Viana, F. Vahid, W. Najjar, E. Barros. A One-Shot Configurable-Cache Tuner for Improved Energy and Performance. IEEE/ACM Design Automation and Test in Europe (DATE), 2007, pp. 755-760.

S. Sirowy, Y. Wu, S Lonardi and F. Vahid. Two Level Microprocessor-Accelerator Partitioning. IEEE/ACM Design Automation and Test in Europe (DATE), 2007, pp. 313-318.

S. Sirowy, Y. Wu, S Lonardi and F. Vahid. Clock-Frequency Partitioning for Multiple Clock Domains Systems-on-a-Chip. IEEE/ACM Design Automation and Test in Europe (DATE), 2007, pp. 397-402.

D. Sheldon, R. Kumar, F. Vahid, D.M. Tullsen, R. Lysecky Conjoining Soft-Core FPGA Processors IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2006, pp. 694-701.

G. Stitt, F. Vahid, W. Najjar A Code Refinement Methodology for Performance-Improved Synthesis from C IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2006, pp. 716-723.

D. Sheldon, R. Kumar, R. Lysecky, F. Vahid, D.M. Tullsen, Application-Specific Customization of Parameterized FPGA Soft-Core Processors IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2006, pp. 261-268.

S. Lysecky, F. Vahid. Automated Application-Specific Tuning of Parameterized Sensor-Based Embedded System Building Blocks Int. Conf. on Ubiquitous Computing (UbiComp), Sep. 2006, pp. 507-524.

S. Lysecky, F. Vahid. Automated Generation of Basic Custom Sensor-Based Embedded Computing Systems Guided by End-User Optimization Criteria Int. Conf. on Ubiquitous Computing (UbiComp), Sep. 2006, pp. 69-86.

R. Lysecky, G. Stitt, F. Vahid. Warp Processors. ACM Transactions on Design Automation of Electronic Systems (TODAES), July 2006, pp. 659-681.

P. Viana, A. Gordon-Ross, E. Keogh, E. Barros, F. Vahid. Configurable Cache Subsetting for Fast Cache Tuning. IEEE/ACM Design Automation Conference (DAC), July 2006, pp. 695 - 700.

G. Stitt, F. Vahid New Decompilation Techniques for Binary-level Co-processor Generation IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2005, pp. 547-554.

A. Gordon-Ross, F. Vahid, N. Dutt. Fast Configurable-Cache Tuning with a Unified Second-Level Cache International Symposium on Low-Power Electronics and Design (ISLPED), Aug. 2005, pp. 323-326.

G. Stitt, F. Vahid, G. McGregor, B. Einloth. Hardware/Software Partitioning of Software Binaries: A Case Study of H.264 Decode International Conference on Hardware/Software Codesign and System Synthesis (CODES/ISSS), Sep. 2005, pp. 285-290.

A. Gordon-Ross and F. Vahid. Frequent Loop Detection Using Efficient Non-Intrusive On-Chip Hardware. IEEE Transactions on Computers, Special Issue-Embedded Systems, Microarchitecture, and Compilation Techniques in Memory of B. Ramakrishna (Bob) Rau, Oct. 2005, Vol. 54, Issue 10, pp 1203-1215.

S. Cotterell and F. Vahid. Usability of State Based Boolean eBlocks. 11th International Conference on Human-Computer Interaction (HCII), 2005, pp.

R. Lysecky, F. Vahid and S. Tan. A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation. IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), 2005, pp. 57-62.

S. Cotterell and F. Vahid. A Logic Block Enabling Logic Configuration by Non-Experts in Sensor Networks. Conference on Human Factors in Computing (CHI), 2005, pp. 1925 - 1928.

C. Zhang, F. Vahid, J. Yang, and W. Najjar. A Way-Halting Cache for Low-Energy High-Performance Systems. ACM Transactions on Architecture and Code Optimization (TACO), Vol. 2, No. 1, March 2005, pp 34-54.

A. Gordon-Ross, F. Vahid, N. Dutt. A First Look at the Interplay of Code Reordering and Configurable Caches. Great Lakes Symposium on VLSI (GLSVLSI), April 2005, pp. 416-421.

S. Cotterell, R. Mannion, F. Vahid, H. Hsieh. eBlocks - An Enabling Technology for Basic Sensor Based Systems IPSN Track on Sensor Platform, Tools and Design Methods for Networked Embedded Systems (SPOTS), April 2005.

C. Zhang, F. Vahid and W. Najjar. A Highly Configurable Cache for Low Energy Embedded Systems. ACM Transactions on Embedded Computing Systems (TECS), Vol. 4, Issue 2, May 2005, pp. 363-387.

R. Lysecky and F. Vahid. A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning. Design Automation and Test in Europe (DATE), March 2005, pp. 18-23.

G. Stitt and F. Vahid. A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms. Design Automation and Test in Europe (DATE), March 2005, pp. 396-397.

R. Mannion, H. Hsieh, S. Cotterell, F. Vahid. System Synthesis for Networks of Programmable Blocks. Design Automation and Test in Europe (DATE), March 2005, pp. 888-893.

G. Stitt, Z. Guo, F. Vahid, and W. Najjar. Techniques for Synthesizing Binaries to an Advanced Register/Memory Structure. ACM/SIGDA Symp. on Field Programmable Gate Arrays (FPGA), Feb. 2005, pp. 118-124.

S. Cotterell, K. Downey, and F. Vahid. Applications and Experiments with eBlocks -- Electronic Blocks for Basic Sensor-Based Systems. IEEE Sensor and Ad Hoc Communications and Networks (SECON), Oct 2004.

C. Zhang, F. Vahid, J. Yang and W. Najjar. A Way-Halting Cache for Low-Energy High-Performance Systems International Symposium on Low-Power Electronics and Design (ISLPED), Aug 2004, pp. 126-131.

R. Lysecky, F. Vahid, and S. Tan. Dynamic FPGA Routing for Just-in-Time FPGA Compilation . Design Automation Conference (DAC), June 2004, pp. 954-959.

A. Gordon-Ross, C. Zhang, F. Vahid. N. Dutt. Tuning caches to applications for low-energy embedded systems. Chapter 6 in Ultra Low-Power Electronics and Design - Kluwer Academic Pub, June 2004.

C. Zhang, F. Vahid and R. Lysecky. A Self-Tuning Cache Architecture for Embedded Systems. ACM Transactions on Embedded Computing Systems (TECS), Vol. 3., Issue 2, May 2004, pp. 407-425.

Z. Guo, W. Najjar, F. Vahid and K. Visssers. A Quantitative Analysis of the Speedup Factors of FPGAs over Processors. ACM/IEEE International Symposium on Field-Programmable Gate Arrays, Feb. 2004.

R. Lysecky and F. Vahid. A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning. Design Automation and Test in Europe Conference (DATE), February 2004, pp. 480-485.

A. Gordon-Ross, F. Vahid and N. Dutt. Automatic Tuning of Two-Level Caches to Embedded Applications. Design Automation and Test in Europe Conference (DATE), February 2004, pp. 208-213.

C. Zhang and F. Vahid. Using a Victim Buffer in an Application-Specific Memory Hierarchy Design Automation and Test in Europe Conference (DATE), February 2004, pp. 220-225.

C. Zhang, F. Vahid and R. Lysecky. A Self-Tuning Cache Architecture for Embedded Systems. Design Automation and Test in Europe Conference (DATE), February 2004, pp. 142-147.

C. Zhang, J. Yang and F. Vahid. Low Static-Power Frequent-Value Data Caches. Design Automation and Test in Europe Conference (DATE), February 2004, pp. 214-219.

G. Stitt, F. Vahid, S. Nemetebaksh. Energy Savings and Speedups from Partitioning Critical Software Loops to Hardware in Embedded Systems. IEEE Transactions on Embedded Computer Systems, January 2004.

C. Zhang, F. Vahid, J. Yang, W. Najjar. A Way-Halting Cache for Low-Energy High-Performance Systems IEEE Computer Architecture Letters, Vol. 2, Sep. 2003.

A. Gordon-Ross and F. Vahid. Frequent Loop Detection Using Efficient Non-Intrusive On-Chip Hardware. ACM/IEEE Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), 2003, pp. 117-124.

S. Cotterell, F. Vahid, W. Najjar and H. Hsieh. First Results with eBlocks: Embedded Systems Building Blocks. ACM/IEEE ISSS/CODES conference, 2003, pp. 168-175.

R. Lysecky and F. Vahid. A Codesigned On-Chip Logic Minimizer. ACM/IEEE ISSS/CODES conference, 2003, pp. 109-113.

A. Gordon-Ross, S. Cotterell, and F. Vahid. Tiny Instruction Caches For Low Power Embedded Systems. ACM Transactions on Embedded Computing Systems, Vol. 2, Issue 4, Nov. 2003, pp. 449-481.

D.C. Suresh, W.A. Najjar, F. Vahid, J.R. Villarreal, G. Stitt. Profiling tools for hardware/software partitioning of embedded applications. Languages, Compilers and Tools for Embedded Systems (LCTES), 2003, pp. 189-198.

C. Zhang, F. Vahid and W. Najjar. A Highly-Configurable Cache Architecture For Embedded Systems. International Symposium on Computer Architecture, 2003, pp. 136-146.

C. Zhang and F. Vahid. Cache Configuration Exploration on Prototyping Platforms. Rapid System Prototyping, 2003, pp. 164-171.

G. Stitt, R. Lysecky and F. Vahid. Dynamic Hardware/Software Partitioning: A First Approach. Design Automation Conference, 2003, pp. 250-255.

R. Lysecky and F. Vahid. On-Chip Logic Minimization. Design Automation Conference, 2003, 334-337.

F. Vahid. Embedded System Design: UCR's Undergraduate Three- Course Sequence Microelectronics Systems Engineering (MSE) conference, 2003.

F. Vahid. The Softening of Hardware IEEE Computer, April 2003, pp. 27-34.

F. Vahid, R. Lysecky, C. Zhang and G. Stitt. Highly Configurable Platforms for Embedded Computing Systems Microelectronics Journal, Elsevier Publishers, Volume 34, Issue 11, November 2003, Pages 1025-1029.

F. Vahid. Making the Best of those Extra Transistors. IEEE Design and Test of Computers, Jan/Feb 2003, pg. 96.

C. Zhang, F. Vahid, W. Najjar. Energy Benefits of a Configurable Line Size Cache for Embedded Systems. IEEE Computer Society Annual Symposium on VLSI, Feb. 2003, pp. 87-91.

T. Givargis and F. Vahid. Platune: A Tuning Framework for System-on-a-Chip Platforms. IEEE Transactions on Computer Aided Design, Vol. 21, No. 11, Nov. 2002, pp. 1317-1327.

T. Givargis, F. Vahid and J. Henkel. Instruction-based System-level Power Evaluation of System-on-a-chip Peripheral Cores. IEEE Transactions on VLSI, pp. 856-863, Vol 10, No 6, Dec. 2002.

F. Vahid, T. Givargis and S. Cotterell. Power Estimator Development for Embedded System Memory Tuning. Journal of Circuits, Systems and Computers, vol. 11, no. 5, pp. 459-476, October 2002.

F. Vahid. Partitioning Sequential Programs for CAD using a Three-Step Approach. ACM Transactions on Design Automation of Electronic Systems, Vol 7, Issue 3, pp 413-429, July 2002.

G. Stitt and F. Vahid. The Energy Advantages of Microprocessor Platforms with On-Chip Configurable Logic. IEEE Design and Test of Computers, November/December 2002, pp. 36-43.

T. Givargis, F. Vahid and J. Henkel. System-level Exploration for Pareto-optimal Configurations in Parameterized System-on-a-chip. IEEE Transactions on VLSI Systems, Vol. 10, Issue 4, Dec. 2002, pp. 416-422.

J. Villarreal, D. Suresh, G. Stitt, F. Vahid and W. Najjar. Improving Software Performance with Configurable Logic. Kluwer Journal on Design Automation of Embedded Systems, November 2002, Volume 7, Issue 4, pp. 325-339.

G. Stitt and F. Vahid. Hardware/Software Partitioning of Software Binaries. IEEE/ACM International Conference on Computer Aided Design, November 2002, pp. 164-170.

S. Cotterell and F. Vahid. Synthesis of Customized Loop Caches for Core-Based Embedded Systems. IEEE/ACM International Conference on Computer Aided Design, November 2002, pp. 655-662.

S. Cotterell and F. Vahid. Tuning of Loop Cache Architectures to Programs in Embedded System Design. IEEE/ACM International Symposium on System Synthesis, October 2002, pp. 8-13.

A. Gordon-Ross and F. Vahid. Dynamic Loop Caching Meets Preloaded Loop Caching -- A Hybrid Approach. International Conference on Computer Design, September 2002, pp. 446-449.

T. Givargis and F. Vahid. Tuning of Cache Ways and Voltage for Low-Energy Embedded System Platforms. Kluwer Journal on Design Automation of Embedded Systems, vol. 7, issue 1-2, pp. 35-51, September 2002.

R. Lysecky, S. Cotterell and F. Vahid. A Fast On-Chip Profiler Memory IEEE/ACM Design Automation Conference, June 2002, pp. 28-33.

B. Grattan, G. Stitt and F. Vahid. Codesign-Extended Applications. IEEE/ACM International Symposium on Hardware/Software Codesign, Estes Park, May 2002, pp. 1-6.

C. Zhang and F. Vahid. A Power-Configurable Bus for Embedded Systems. IEEE International Symposium on Circuits and Systems, Scottsdale, May 2002, pp.V-809-812.

G. Stitt, B. Grattan, J. Villarreal and F. Vahid. Using On-Chip Configurable Logic to Reduce Embedded System Software Energy. IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa Valley, April 2002, pp. 143-151.

G. Stitt and F. Vahid. Propagating Constants Past Software to Hardware Peripherals in Fixed-Application Embedded Systems. In book "Compilers and operating systems for low power," editors L. Benini, M. Kandemir, J. Ramanujam, Kluwer Academic Publishers, 2003, Chapter 7, pp. 115-136.

A. Gordon-Ross, S. Cotterell and F. Vahid. Exploiting Fixed Programs in Embedded Systems: A Loop Cache Example. IEEE Computer Architecture Letters, Vol 1, January 2002.

R. Lysecky and F. Vahid. Prefetching for Improved Bus Wrapper Performance in Cores. ACM Transactions on Design Automation of Electronic Systems, Vol. 7, No. 1, pp. 58-90, January 2002.

F. Vahid, R. Patel and G. Stitt. Propagating Constants Past Software to Hardware Peripherals in Fixed-Application Embedded Systems. Special Issue of ACM SIGARCH Newsletter, Dec. 2001. Selected for special issue from earlier version of paper in Compilers and Operating Systems for Low Power (COLP'01).

T. Givargis and F. Vahid and J. Henkel. System-level Exploration for Pareto-optimal Configurations in Parameterized Systems-on-a-chip. International Conference on Computer Aided Design, Nov 2001, pp. 25-30.

T. Givargis, F. Vahid and J. Henkel. Evaluating Power Consumption of Parameterized Cache and Bus Architectures in System-on-a-Chip Designs. IEEE Transactions on VLSI, Vol 9, No. 4, pp. 500-508, Aug 2001.

F. Vahid and A. Gordon-Ross. A Self-Optimizing Embedded Microprocessor using a Loop Table for Low Power. International Symposium on Low Power Electronics and Design, Aug 2001, pp. 219-224.

F. Vahid and T. Givargis. Platform Tuning for Embedded Systems Design. IEEE Computer, Vol. 34, No. 3, pp. 112-114, March 2001.

T. Givargis, F. Vahid and J. Henkel. Trace-driven System-level Power Evaluation of System-on-a-chip Peripheral Cores. Asia South-Pacific Design Automation Conference (ASP-DAC), pp. 306-311, January 2001.

G. Stitt, F. Vahid, T. Givargis, R. Lysecky. A First-step Towards an Architecture Tuning Methodology for Low Power. Compilers, Architectures, and Synthesis for Embedded Systems (CASES'00), pp. 187-192, November 2000.

T. Givargis, F. Vahid and J. Henkel. Instruction-based System-level Power Evaluation of System-on-a-chip Peripheral Cores. IEEE/ACM International Symposium on System Synthesis (ISSS), pp. 163-169, September 2000.

R. Lysecky, F. Vahid, T. Givargis. Experiments with the Peripheral Virtual Component Interface. International Symposium on System Synthesis (ISSS), pp. 221-224, September 2000.

T. Givargis and F. Vahid. Parameterized System Design IEEE/ACM International Workshop on Hardware/Software Codesign (CODES), pp. 98-102, May 2000.

T. Givargis, F. Vahid and J. Henkel. Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design. Design Automation and Test in Europe (DATE) Conference pp. 334-338, March 2000.

R. Lysecky, F. Vahid, T. Givargis. Techniques for Reducing Read Latency of Core Bus Wrappers. Design Automation and Test in Europe (DATE) Conference pp. 84-91, March 2000. Best Paper Award.

T. Givargis, F. Vahid and J. Henkel. A Hybrid Approach for Core-Based System-Level Power Modeling. Asia South-Pacific Design Automation Conference (ASP-DAC), pp. 141-145, January 2000.

T. Givargis, J. Henkel and F. Vahid. Interface and Cache Power Exploration for Core-Based Embedded System. International Conference on Computer-Aided Design (ICCAD), pp. 270-273, November 1999.

R. Lysecky, F. Vahid, T. Givargis, and R. Patel. Pre-fetching for Improved Core Interfacing. International Symposium on System Synthesis (ISSS), pp. 51-55, November 1999.

F. Vahid and T. Givargis. The Case for a Configure-and-Execute Paradigm. International Workshop on Hardware/Software Codesign (CODES), pp. 59-63, May 1999.

E. Hwang and F. Vahid and Y.C. Hsu. FSMD Functional Partitioning for Low Power Design Automation and Test in Europe (DATE) Conference pp. 22-28, March 1999.

F. Vahid. Techniques for Minimizing and Balancing I/O during Functional Partitioning IEEE Transactions on CAD, Vol. 18, No. 1, pp. 69-75 January 1999.

F. Vahid. Procedure Cloning: A Transformation for Improved System-Level Functional Partitioning ACM Transactions on Design Automation of Electronic Systems, Volume 4, Number 1, pp. 70-96, 1999.

F. Vahid. A Three-Step Approach to the Functional Partitioning of Large Behavioral Processes International Symposium on System Synthesis, pp. 152--157, December 1998.

F. Vahid and T. Givargis. Incorporating Cores into System-Level Specification. International Symposium on System Synthesis (ISSS), pp. 43--48, December 1998.

T. Givargis and F. Vahid. Interface Exploration for Reduced Power in Core-Based Systems. International Symposium on System Synthesis (ISSS), pp. 117--122, December 1998.

D. Gajski, F. Vahid, S. Narayan and J. Gong. System-Level Exploration with SpecSyn Design Automation Conference, pp. 812-817, June 1998.

F. Vahid, T.D.M. Le and Y.C. Hsu. Functional Partitioning Improvements over Structural Partitioning for Packaging Constraints and Synthesis-tool Performance ACM Transactions on Design Automation of Electronic Systems, Volume 3, Number 2, pp. 181-208, 1998.

D.D. Gajski and F. Vahid and S. Narayan and J. Gong. SpecSyn: An Environment Supporting the Specify-Explore-Refine Paradigm for Hardware/Software System Design IEEE Transactions on VLSI Systems, Vol. 6, No. 1, pp. 84-100, 1998. Awarded the IEEE VLSI Transactions Best Paper Award, June 2000.

F. Vahid and S. Narayan. Guest Editors' Introduction to the Special Issue on ISSS'96 ACM Transactions on the Design Automation of Electronic Systems, Vol. 2, No. 4, Oct. 1997, pp. 307-311.

F. Vahid. Port Calling: A Transformation for Reducing I/O during Multi-Package Functional Partitioning International Symposium on System Synthesis, pp. 107--112, September 1997.

L. Tauro and F. Vahid. Message-Based Hardware/Software Communication in HDL/C Environments Asia-Pacific Conference on Hardware Description Languages ASP-CHDL), August 1997.

F. Vahid and L. Tauro. An Object-Oriented Communication Library for Hardware-Software Co-Design International Workshop on Hardware/Software Codesign (CODES), pp. 81--86, March 1997.

F. Vahid and T.D.M. Le. Extending the Kernighan/Lin Heuristic for Hardware and Software Functional Partitioning Kluwer Journal on Design Automation of Embedded Systems, Vol. 2, No. 2, pp. 237-261, March 1997.

F. Vahid. Procedure Cloning: A Transformation for Improved System-Level Functional Partitioning European Design and Test Conference, pp. 487--492, March 1997.

F. Vahid. Modifying Min-Cut for Hardware and Software Functional Partitioning International Workshop on Hardware/Software Codesign, pp. 43--48, March 1997.

F. Vahid. I/O and Performance Tradeoffs with the FunctionBus during Multi-FPGA Partitioning International Symposium on Field-Programmable Gate Arrays, pp. 27-34, February 1997.

F. Vahid and T.D.M. Le and Y.C. Hsu. A Comparison of Functional and Structural Partitioning International Symposium on System Synthesis, pp. 121-126, November 1996.

F. Vahid and T.D.M. Le. Towards a Model for Hardware and Software Functional Partitioning International Workshop on Hardware/Software Codesign, pp. 116-123, March 1996.

D. Gajski and S. Narayan and L. Ramachandran and F. Vahid and P. Fung. System Design Methodologies: Aiming at the 100 h Design Cycle IEEE Transactions on VLSI Systems, Vol. 4, No. 1, pp. 70-82, 1996.

F. Vahid and D.D. Gajski. Closeness Metrics for System-Level Functional Partitioning European Design Automation Conference, pp. 328-333, September 1995.

F. Vahid and D.D. Gajski. Clustering for Improved System-Level Functional Partitioning International Symposium on System Synthesis, pp. 28-33, September 1995.

F. Vahid. Procedure Exlining: A Transformation for Improved System and Behavioral Synthesis International Symposium on System Synthesis, pp. 84-89, September 1995.

F. Vahid. Procedure Exlining: A New System-Level Specification Transformation European Design Automation Conference -- EuroVHDL, pp. 508-513, September 1995.

F. Vahid and D. Gajski. Incremental Hardware Estimation during Hardware/Software Functional Partitioning IEEE Transactions on VLSI Systems, Vol. 3, No. 3, pp. 459-464, September 1995.

F. Vahid and S. Narayan and D. Gajski. SpecCharts: A VHDL Front-End for Embedded Systems IEEE Transactions on CAD, Vol. 14, No. 6, pp. 694-706, 1995.

F. Vahid and D.D. Gajski. SLIF: A Specification-Level Intermediate Format For System Design European Design and Test Conference, pp. 185-189, March 1995.

D. Gajski and F. Vahid. Specification and Design of Embedded Software-Hardware Systems IEEE Design & Test of Computers, Vol. 12, No. 1, Spring 1995, pp. 53-67.

F. Vahid and J. Gong and D.D. Gajski. A Binary-Constraint Search Algorithm for Minimizing Hardware during Hardware-Software Partitioning European Design Automation Conference -- EuroDAC, pp. 214-219, September 1994.

F. Vahid, S. Narayan and D.D. Gajski. A Transformation Integrating VHDL Behavioral Specification with Synthesis and Software Generation European Design Automation Conference -- EuroDAC, pp. 552-557, September 1994.

D.D. Gajski and F. Vahid and S. Narayan. A System-Design Methodology: Executable-Specification Refinement European Conference on Design Automation, pp. 458-463, March 1994.

D.D. Gajski and F. Vahid and S. Narayan and J. Gong BOOK: Specification and Design of Embedded Systems Title page, Contents, and Preface Online slides Prentice Hall, 1994. Perhaps the first textbook on embedded system design.

F. Vahid, and D. Gajski. Specification Partitioning for System Design Design Automation Conference, pp. 219-224, June 1992.

Pubs from before 1994 not listed.