Note: You must first set up Synopsys environment variables as described in 
the synopsys_simulation.txt file. Then:

 a) Login to synthesis. It has 10 Synopsys licenses.
         %   ssh synthesis
         %   setenv DISPLAY your_machine_name:0        // set your display
                NOTE: bash users do the following:
                   export DISPLAY = your_machine_name:0
         % source $SYNOPSYS/admin/install/sim/bin/environ.csh
                NOTE: bash users do the following: (.sh instead of.csh)
                   source $SYNOPSYS/admin/install/sim/bin/environ.sh


 b) create a directory where you will work and make that your current directory.
    This directory will contain your VHDL source code.
    % mkdir binary
    % cd binary
    % mkdir work

 c) copy the technology library that you'll use for the compilation into your
    work directory and call it "your_library.db". NB you have to use the name
    "your_library.db"
    % cp $SYNOPSYS/libraries/syn/class.db your_library.db 

 d) write your VHDL source code and saves it.
    % vi binary.vhd           // using "binary.vhd" as an example

 e) start the synthesis shell.
    % dc_shell

 f) Analyzes your VHDL file and change it to intermediate format.
    dc_shell> analyze -format vhdl -lib WORK binary.vhd

 g) Builds the design from the intermediate format.
    dc_shell> elaborate binary // "binary" is the design name
                               // in your VHDL source file.

 h) compile the design into gate level netlist.
    dc_shell> compile

 i) write the gate level netlist to a file.
    dc_shell> write -format vhdl -output binary_gate.vhd

 j) to get help on any of the commands
    dc_shell> help command_name
    dc_shell> help analyze

 k) exit the shell
    dc_shell> quit


Appendix: To view the online documents
   % setenv DISPLAY your_machine_name:0        // set your display
   % sold

   select File, Open Collection
   select Synopsys Synthesis Tools or Synopsys Simulation Tools
   click OK