library IEEE;
use IEEE.std_logic_1164.all;

entity f1test is
end f1test;

architecture testbench of f1test is

   component f1 
      port (x,y,z: in std_logic; f: out std_logic);
   end component;
   
   signal x_sig, y_sig, z_sig, f_sig: std_logic;

   for all: f1 use entity work.f1(beh); 
   -- change to "struct" to test the structural architecture for f1

begin

   f1_1 : f1 port map (x_sig,y_sig,z_sig,f_sig);

   MainTestProcess: process
   begin
      x_sig <= '0'; y_sig <= '0'; z_sig <= '0';
      wait for 5 ns;
      assert (f_sig='0') report "failed test 000" severity error;
      wait for 5 ns;

      x_sig <= '0'; y_sig <= '0'; z_sig <= '1';
      wait for 5 ns;
      assert (f_sig='0') report "failed test 001" severity error;
      wait for 5 ns;

      x_sig <= '0'; y_sig <= '1'; z_sig <= '0';
      wait for 5 ns;
      assert (f_sig='0') report "failed test 010" severity error;
      wait for 5 ns;

      x_sig <= '0'; y_sig <= '1'; z_sig <= '1';
      wait for 5 ns;
      assert (f_sig='1') report "failed test 011" severity error;
      wait for 5 ns;

      x_sig <= '1'; y_sig <= '0'; z_sig <= '0';
      wait for 5 ns;
      assert (f_sig='0') report "failed test 100" severity error;
      wait for 5 ns;

      x_sig <= '1'; y_sig <= '0'; z_sig <= '1';
      wait for 5 ns;
      assert (f_sig='1') report "failed test 101" severity error;
      wait for 5 ns;

      x_sig <= '1'; y_sig <= '1'; z_sig <= '0';
      wait for 5 ns;
      assert (f_sig='1') report "failed test 110" severity error;
      wait for 5 ns;

      x_sig <= '1'; y_sig <= '1'; z_sig <= '1';
      wait for 5 ns;
      assert (f_sig='1') report "failed test 111" severity error;
      wait for 5 ns;

      wait; -- end of test process

   end process; 

end;