library IEEE;
use IEEE.std_logic_1164.all;

entity f1 is
  port (
          x,y,z: in std_logic;
          f: out std_logic
       );
end f1;

architecture struct of f1 is

   component and2
      port ( x,y: in std_logic; f: out std_logic);
   end component;
   component or3
      port ( x,y,z: in std_logic; f: out std_logic);
   end component;

   for all: and2 use entity work.and2(beh);
   for all: or3 use entity work.or3(beh);

   signal n1, n2, n3 : std_logic;

begin

   and2_1 : and2 port map (x, y, n1);
   and2_2 : and2 port map (x, z, n2);
   and2_3 : and2 port map (y, z, n3);
   or3_1  : or3  port map (n1,n2,n3,f);
   
end;