1. Test the behavioral description of f1:

   vhdlan f1.vhdl
   vhdlan f1test.vhdl
   vhdldbx f1test
      trace the signals, run at increments of 10, check output
      Note that the last assertion fails -- we forgot: x and y and z.  
      Fix f1.vhdl, re-analyze and re-run vhdldbx

2. Design and test the structural implementation of f1:
   
   Design structure and capture in f1_struct.vhdl
   Edit f1test.vhdl to use the 'struct' architecture rather than 'beh'
   vhdlan and2.vhdl
   vhdlan or3.vhdl
   vhdlan f1_struct.vhdl
   vhdlan f1test.vhdl
   vhdldbx f1test
      trace the signals, run at increments of 10, check output
   
   
3. Use Synopsys Design Compiler to synthesize f1 behavior to structure instead.

   dc_shell
   analyze -format vhdl -lib WORK f1.vhdl
   elaborate f1
   compile
   write -format vhdl -output f1_gate.vhdl
   Edit f1_gate.vhdl and try to understand the synthesized design
  
   Use design_analyzer to do the same graphically