library IEEE;
use IEEE.std_logic_1164.all;

-- f1 should set f to 1 whenever there's two or more 1's on the inputs
entity f1 is
  port (
          x,y,z: in std_logic;
          f: out std_logic
       );
end f1;

architecture beh of f1 is

begin

   process (x,y,z)
   begin
      -- NOTE: something's wrong with this function.   Simulate and 
      --       then fix it.
      f <= ( (not x) and y and z)  or ( x and (not y) and z) or 
           ( x and y and (not z) ) ;
   end process;
   
end;