library IEEE;
use IEEE.std_logic_1164.all;

entity and2test is
end and2test;

architecture testbench of and2test is

   component and2 
      port (x,y: in std_logic; f: out std_logic);
   end component;
   
   signal x_sig, y_sig, f_sig: std_logic;

   for all: and2 use entity work.and2(beh); 

begin

   and2_1 : and2 port map (x_sig,y_sig,f_sig);

   MainTestProcess: process
   begin
      x_sig <= '0'; y_sig <= '0'; 
      wait for 10 ns;
      x_sig <= '0'; y_sig <= '1'; 
      wait for 10 ns;
      x_sig <= '1'; y_sig <= '0'; 
      wait for 10 ns;
      x_sig <= '1'; y_sig <= '1'; 
    
      wait; -- end of test process

   end process; 

end;