library IEEE,lsi_10k;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use lsi_10k.COMPONENTS.all;

package CONV_PACK_DECODE is

-- define attributes
attribute ENUM_ENCODING : STRING;

-- define any necessary types
--type UNSIGNED is array (INTEGER range <>) of std_logic;

end CONV_PACK_DECODE;

library IEEE,lsi_10k;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use lsi_10k.COMPONENTS.all;

use work.CONV_PACK_DECODE.all;

entity DECODE is

   port( input : in UNSIGNED (2 downto 0);  output : out UNSIGNED (7 downto 0)
         );

end DECODE;

architecture SYN of DECODE is

   component NR3
      port( A, B, C : in std_logic;  Z : out std_logic);
   end component;
   
   component NR2
      port( A, B : in std_logic;  Z : out std_logic);
   end component;
   
   component AN3
      port( A, B, C : in std_logic;  Z : out std_logic);
   end component;
   
   component ND2
      port( A, B : in std_logic;  Z : out std_logic);
   end component;
   
   component IV
      port( A : in std_logic;  Z : out std_logic);
   end component;
   
   signal n7, n8, n9, n10, n11, n12 : std_logic;

begin
   
   U6 : NR3 port map( A => n7, B => n8, C => n9, Z => output(7));
   U7 : NR2 port map( A => n7, B => n10, Z => output(6));
   U8 : NR2 port map( A => n7, B => n11, Z => output(5));
   U9 : NR3 port map( A => input(0), B => input(1), C => n7, Z => output(4));
   U10 : AN3 port map( A => input(1), B => n7, C => input(0), Z => output(3));
   U11 : NR2 port map( A => input(2), B => n10, Z => output(2));
   U12 : NR2 port map( A => input(2), B => n11, Z => output(1));
   U13 : NR3 port map( A => n8, B => input(2), C => input(0), Z => output(0));
   U14 : ND2 port map( A => n10, B => n11, Z => n8);
   U15 : IV port map( A => input(2), Z => n7);
   U16 : IV port map( A => input(0), Z => n9);
   U17 : ND2 port map( A => input(1), B => n9, Z => n10);
   U18 : ND2 port map( A => input(0), B => n12, Z => n11);
   U19 : IV port map( A => input(1), Z => n12);

end SYN;