Course Project.

Project Description

The course project is designed to provide students with the experience of implementing a small core. For this project, students will work alone or in groups of two or three to design and test their implementation of a standard core.

Each student or group must choose a core that they want to design and submit thier proposed design to the instructor via e-mail. The instructor will then confirm the group composition and their choice of core assuming it is suitable for the size of the group and is not already taken by another student or group.

The following provides a list of cores that the students may select from. If you would like to choose a core from outside this list, please consult with the instructor.

List of Cores

Project Requirements

• Synthesizable VHDL description of the selected core.
• Synthesized version of the core.
• Testbench(es) used to verify the correct functionality of both the behavioral and synthesized designs.