--
-- Copyright (c) 1999-2000 Tony Givargis.  Permission to copy is granted
-- provided that this header remains intact.  This software is provided
-- with no warranties.
--
-- Version : 2.6
--

-------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;

-------------------------------------------------------------------------------

entity DIVIDER is
    port(src_1  : in  UNSIGNED (7 downto 0);
         src_2  : in  UNSIGNED (7 downto 0);
         des_1  : out UNSIGNED (7 downto 0);
         des_2  : out UNSIGNED (7 downto 0);
         des_ov : out STD_LOGIC);
end DIVIDER;

-------------------------------------------------------------------------------

architecture BHV of DIVIDER is

    constant C0_8 : UNSIGNED(7 downto 0) := "00000000";
    constant C1_8 : UNSIGNED(7 downto 0) := "00000001";
    constant CD_8 : UNSIGNED(7 downto 0) := "--------";

    procedure DO_DIV(a, b : in UNSIGNED (7 downto 0);
                     r : out UNSIGNED (15 downto 0);
                     ov : out STD_LOGIC) is
    
        variable v1 : UNSIGNED (15 downto 0);
        variable v2, v3 : UNSIGNED (8 downto 0);
    begin
        if( b = C0_8 ) then
            
            r(7 downto 0) := CD_8;
            r(15 downto 8) := CD_8;
            ov := '1';
        elsif( a = b ) then

            r(7 downto 0) := C1_8;
            r(15 downto 8) := C0_8;
            ov := '0';
        elsif( a < b ) then

            r(7 downto 0) := C0_8;
            r(15 downto 8) := src_1;
            ov := '0';
        else

            v1(7 downto 0) := a;
            v1(15 downto 8) := C0_8;
            v3 := "0" & b;
            for i in 0 to 7 loop

                v1(15 downto 1) := v1(14 downto 0);
                v1(0) := '0';
                v2 := "1" & v1(15 downto 8);
                v2 := v2 - v3;
                if( v2(8) = '1' ) then
                    
                    v1(0) := '1';
                    v1(15 downto 8) := v2(7 downto 0);
                end if;
            end loop;

            r := v1;
            ov := '0';
        end if;
    end DO_DIV;
    
begin
    process(src_1, src_2)

        variable v16 : UNSIGNED (15 downto 0);
        variable v_ov : STD_LOGIC;
    begin
        DO_DIV(src_1, src_2, v16, v_ov);
        des_1 <= v16(7 downto 0);
        des_2 <= v16(15 downto 8);
        des_ov <= v_ov;
    end process;
end BHV;

-------------------------------------------------------------------------------

-- end of file --