Assignemnt 1 - Simple ALU design.

Design Specifications

In this assignment, you will design a simple ALU with 8 operations. The following image provides a black box view of the ALU, defining its inputs and outputs.

Likewise, the following is the corresponding entity declaration for the ALU that you are required to use. 

entity ALU is
    port( input1 : in  UNSIGNED(15 downto 0);
          input2 : in  UNSIGNED(15 downto 0);
          oper   : in  UNSIGNED(2 downto 0);
          output : out UNSIGNED(15 downto 0));
end ALU;

The operations supported by the ALU are defined as follows:

000 - input1 >> 1 (shift right)
001 - input1 << 1 (shift left)
010 - input1 + input2
011 - input1 - input2
100 - input1 * input2 (lower 16-bits of the 32-bit result)
101 - input1 == input2 (1 if true, 0 if false)
110 - input1 < input2 (1 if true, 0 if false)
111 - input1 > input2 (1 if true, 0 if false)

Once you have tested your design using a testbench at the behavioral level, you need to synthesize your design and test the gate-level output using the same testbench. If the syntehsized version passes the testbench with the same output you have completed your assignemnt. Otherwise, you must fix your behavioral design such that the synthesized version is correct.

Assignment Requirements