UCR CS 179: Project in Architecture/Embedded Systems

UCR CS 179J: Project in Architecture / Embedded Systems, Spring 2004

Overview

Catalog Description: Discussion, one hour; laboratory, nine hours. Prerequisite(s): CS 141, CS 122A, and CS 161 with a grade of "C-" or better; Under the direction of a faculty member, students (individually or in small teams with shared responsibilities) propose, design, build, test, and document software and/or hardware devices or systems. Requires a written report, giving details of the project and test results, and an oral presentation of the design aspects. Emphasizes teamwork, making technical presentations, and developing oral and written communication skills.

Previous Offering (CS179J Winter 04)

Basic Information

Instructor and office hours
Prof. Frank Vahid (vahid@cs.ucr.edu)
Office Hrs:
Office Location: Surge 328

Teaching Assistant
Greg Stitt (gstitt@cs.ucr.edu)
Office Hrs: By appointment

Discussion
Wednesday, 10:10 - 11:00
PHY 2104

Lab
TBA

Textbooks
Required: The Art of Designing Embedded Systems, J. Ganssle, 1st ed., 1999, Newnes Press, Butterworth-Heinemann.
Required: The Seven Habits of Highly-Effective People, Stephen R. Covey, Simon & Schuster, any edition. (You can find this book online easily and at a low price -- order it early in the quarter, and we'll use it a few weeks into the quarter)

Grade Breakdown
10%: Weekly participation
10%: Online logs and homeworks
10%: Quizzes
5%: Tradeoff analysis
5%: Proposal
15%: First prototype and presentation
15%: Second prototype and presentation
15%: Final implementation
15%: Final report, presentation and interview

Students must keep a weekly log that includes hours spent, tasks, issues, and plans. Logs for a week should be done by Friday at 3:00 -- best to update logs daily though. Keeping a log is good engineering practice. Here is a sample of a good log from a previous quarter: Sample Student Log. Please copy the format (save as html, then edit the html). Students should provide the TA with the log's URL, which should be in their UCR account (no off-campus URLs).

You'll be submitting a tradeoff analysis of possible design options early in the quarter. Here's a sample of a nice tradeoff analysis from a previous quarter: Sample Tradeoff Analysis.

Course email list

CS 179J mailing List ( send mail now or access the archive): Be sure to sign up to receive important announcements, which may be made only through the course email list. You must use your CS or EE account, or else some other UCR account, so be sure to learn how to read those accounts or at least automatically forward messages to your personal email address (just create in your home directory a file named ".forward" containing your personal email address). It is preferable to use your CS/EE/UCR account when communicating with your instructor and TA.

Lab Information

Project Options Description

JPEG Decoder Implement a JPEG decoder. The decoder will display images on a computer monitor using a VGA interface that you will implement in an FPGA. The remaining parts of the JPEG decoder will be implemented in software running on an embedded microprocessor. The decoder should support multiple images and provide an interface to allow users to view a slideshow.

Configurable Logic Fabric (FPGA) design/simulator Create a simulator, written in either C/C++ or VHDL, for a specified FPGA fabric. The design/simulator should provide a cycle-accurate simulation of I/O, switch matrices, configurable logic blocks, and interconnect. The C++ simulator should be integrated into SimpleScalar to allow for a complete simulation of hardware and software. The VHDL simulator should be synthesized and implemented on an FPGA. Details on the FPGA fabric can be found here.

Schedule (subject to change)

Schedule
Week 1 March 29 - April 2

   Introduction

   READ and study the domain of your project, think about implementation issues and hardware you'll need.

Week 2 April 5 - April 9

   Tradeoff analysis due on your web log page before class.

Week 3 April 12 - April 16 Each of the following is due before class on your web log site:

   Parts List Due (html format)- don't forget to include vendor name, vendor contact, part number, and cost.

   Written project proposal due (html or pdf format)- Post your project proposal with analysis of tradeoffs, time estimation, project cost, complexity. Make sure to describe how you plan on implementing every part of your project. For group proposals, the role of each individual must be clearly specified, and all members must help write the proposal (with authors of sections clearly indicated)

Homework 1

Week 4 April 19 - April 23 Quiz 1 (on textbook material, and project domain). Book and project discussion.

Week 5 April 26 - April 30

   1st Prototype Due - Demo to class

Grades as of 4/29.

Week 6 May 3 - May 7 Discussion of "Seven Habits of Highly-Effective People"

Week 7 May 10 - May 14

   2nd Prototype Due - Demo to class

Online turnin.

Week 8 May 17 - May 21 Quiz 2 on 7 Habits and on project domain.

Week 9 May 24 - May 28

   Full functionality should be implemented

   Polishing and documentation

Grades as of 5/28.

Week 10 May 31 - June 4

   Final project report and presentations

   Proejct report, schematics, and code should be submitted, turn-in will be setup

   Return all parts checked-out/used by Friday

Finals June 7 - June 12

April 2004 May 2004 June 2004

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Available Hardware

Xilinx XS40 (8051, FPGA)

Triscend E5 (8051, FPGA)

Breadboard

As part of your project, you may need to order additional parts. You may request a small budget for your group.

Helpful Links
Xilinx

Ordering Parts
Below are a couple of places you can find parts:
Jameco Electronics
Digi-Key Corporation
Mouser Electronics

When specifying which parts are needed be sure to include where to order the parts, part number, description, and cost.

Class Logs

Project Options	Description
JPEG Decoder	Implement a JPEG decoder. The decoder will display images on a computer monitor using a VGA interface that you will implement in an FPGA. The remaining parts of the JPEG decoder will be implemented in software running on an embedded microprocessor. The decoder should support multiple images and provide an interface to allow users to view a slideshow.
Configurable Logic Fabric (FPGA) design/simulator	Create a simulator, written in either C/C++ or VHDL, for a specified FPGA fabric. The design/simulator should provide a cycle-accurate simulation of I/O, switch matrices, configurable logic blocks, and interconnect. The C++ simulator should be integrated into SimpleScalar to allow for a complete simulation of hardware and software. The VHDL simulator should be synthesized and implemented on an FPGA. Details on the FPGA fabric can be found here.