Using Synopsys Tools

Setting up your account

The first step in the design of the system involves the syntax checking of your VHDL code. To do this, insure that there is an empty directory called "work" in your project directory, and then type: vhdlan <filename> -- This will run the Synopsys VHDL analysis tool, which will check your code to insure that it is valid according to the appropriate VHDL syntax.
After you have compiled both the code for the system and for the testbench, it is time to actually simulate the design and insure proper functionality. This is done by typing "vhdldbx". This will bring up the Synopsys VHDL Debugger. Now select the appropriate configuration for the entity that you wish to simulate (the testbench entity for example). Wait till the VHDL code is displayed in the upper-half of the window. From the "Misc" pull-down menu select the "Hierarchy Browser". This will bring up the VSS Hierarchy Browser, which allows you to trace the signals present in your entity. You will see a green arrow pointing at the top level entity you decided to simulate. Clicking next to this arrow will reveal any components which comprise the entity. Select the signals that you wish to trace, and double-click on the first signal. This will bring up the Synopsys Waveform Viewer, and the bottom half of the VHDL debugger will indicate that the signal is being traced. Put in the time that you wish the simulation to run for in the "Run" window, and hit the "Run" button to simulate for the specified time.

compile.scr

example.scr

Now you must modify the example_syn.scr file to reflect the core that you are attempting to synthesize. Locate all instances of the word "EXAMPLE" in the example_syn.scr file and replace this with the name of the core that you wish to synthesize. For example, if you were synthesizing an entity called decoder, you would replace the text "EXAMPLE.vhd" with "DECODER.vhd". Rename the file to "your_core_name_syn.scr".

Type "dc_shell" to start the Synopsys synthesis development environment.
Now type "include your_core_name_syn.scr". This will carry out a variety of tasks and will then output a file entitled your_core_name_GATE.db which is a file used internally by Synopsys, and a file called your_core_name_GATE.vhd
You must now edit the your_core_name_GATE.vhd file in the following manner:

Now you can re-simulate the entity and select the configuration for the synthesized entity to insure that the synthesized design works as expected.

This example will show how to do use the Synopsys tools to analyze, simulate, synthesize and then re-simulate a real combinational logic device, namely a 3 to 8 decoder.
Copy the following files into your project directory:

Make sure that you have created a "work" directory, then analyze the files by typing:

Type "vhdldbx"
Highlight "CFG_DECOD_TB" as the design you want to simulate, and click on "OK"
Wait until you see the VHDL code for the decoder testbench in the main window and then click on the "Misc" pull-down menu and select "Hierarchy Browser".
You should now see the VSS Hierarchy Browser window. Click on the DECOD_TB entity, this will reveal the input/output signals in the DECOD_TB entity.
Double-click on INPUT_i and wait until the Synopsys Waveform Viewer window pops up.
Now Double-click on OUTPUT_o signal to also trace this signal.
In the main Vhdldbx debugger window enter a value of 100 for the "Run" input window. This indicates that we want to perform a simulation for 100 ns.
Now click on the "Run" button to start the simulation. You should now see the various test cases in the testbench revealed in waveform format. Click on the bar with arrows pointing in both directions, which will allow you to click on and move the vertical red bar. You can now move the bar left and right and view the values for INPUT_I and OUTPUT_O in the middle window. Carefully investigate the waveform to ensure that the 3 to 8 decoder works as expected.
Now you must synthesize the decoder. To do this type "dc_shell". When you are at the "dc_shell" prompt type "include decod_syn.scr"
Now edit the decoder gate file (DECOD_GATE.vhd). Comment out the line "type UNSIGNED is array (INTEGER range<>) of STD_LOGIC;" and add the following code to the end of the file

analyze the gate level decoder file --- type "vhdlan DECOD_GATE.vhd"
modify the testbench so that it uses the synthesized decoder instead of the behavioral version. To do this edit the configuraiton of the testbench entity by editing:

analyze the decoder testbench -- type "vhdlan DECODE_TB.vhd"
re-run the simulation process --- type "vhdldbx"
Carry out the simulation process described above and make sure that the synthesized version of the decoder works as well.