UCR CS 122B
Winter 2004
Prof. Frank Vahid

Homework 2
Due Thursday, 1/29/04, at the beginning of lecture.

For any problem, if you need to make assumptions not stated in the
problem, list them explicitly. You may find that drawing your circuits
using a computer (e.g., Word) may be more convenient than hand-drawing
the circuits, though we'll accept neatly hand-drawn circuits.

1. (4 points) Create a simple configurable logic fabric having two 
              3-input 2-output Configurable Logic Blocks (CLBs), each 
              consisting of a single Lookup Table (LUT) implemented 
              using an 8x2 RAM. CLB 1's inputs come from external pins, 
              and its two outputs connect to a switch matrix. The switch 
              matrix has two inputs and two outputs. All four possible 
              mappings of the two inputs to the two outputs are possible,
              configured by four internal D flip-flops.  The two outputs 
              of the switch matrix connect to two inputs of CLB 2. CLB 2's
              third input comes from an external pin. CLB 2's two outputs
              connect to external pins.  Draw this fabric.  Show the internals
              of the CLBs and switch matrices; for the RAM, show the internals
              merely as 16 D flip-flops -- you need not show other RAM 
              internal logic.

2. (2 points) Configurable logic is typically programmed using a 
              "scan chain." All flip-flops (those in the LUT RAMs and the
              switch matrices) can be configured as one long shift register.
              An external pin, say "prog," activates the shift register
              formation, meaning the flip-flops will get their input from
              the previous flip-flop in the long shift register, rather
              than from normal input. A second external pin, "progdata,"
              will contain the bitstream to be serially programmed into the
              configurable logic fabric.  Update your drawing from problem 1
              to represent the scan chain. Hint: add 2x1 muxes in front of
              every flip-flop.
               
3. (2 points) A 2-bit adder adds two 2-bit numbers, a1a0 + b1b0, and 
              generates a carry and sum output (assume no external 
              carry-in bit to the 2-bit adder). Using logic gates, draw
              the internal design of a 2-bit adder (Hint: use two
              full-adders).

4. (2 points) Partition your circuit from problem 3 into two groups (draw
              a circle around the components in each group), and indicate
              to which CLB each group will be mapped. Clearly list the
              number of inputs and outputs of each group.

5. (3 points) Update your diagram from problem 1 (or 2) to show the content
              of every D flip-flop in your configurable logic, and the
              connections of a1, a0, b1, b0, carry and sum to external pins,
              in order to implement a 2-bit adder on your logic. 

6. (2 points) Show the bitstream necessary to program your logic -- be 
              careful that your bitstream is in the same order as your
              shift register requires. 

7. (1 point)  How many cycles would your configurable logic require to 
              program, and why?

8. (4 points) Roughly compare the performance (give the speedups of the 
              faster two compared to the slowest) of a 32-tap FIR filter 
              on the following architectures:
              (a) A 200 MHz microprocessor that executes 1 instruction 
                  every cycle, except with a 4-cycle multiply instruction.
              (b) A 200 MHz digital signal processor that executes 
                  1 instruction every cycle, and has a special 
                  single-cycle multiply-accumulate (MAC) instruction that 
                  can perform the following computation in just : x = x + c*y.
              (c) A 100 MHz FPGA that has as many gates as we could possibly
                  need, and can perform a multiplication in 1 cycle.
                 

Collaboration is strong encouraged. 5% extra credit for groups of 3 or more
-- list your partners' names on your submission.