The 8051 memory architecture includes 128 bytes of data memory that are accessible directly by its instructions. A 32-byte segment of this 128 byte memory block is bit addressable by a subset of the 8051 instructions, namely the bit-instructions. External memory of up to 64 Kbytes is accessable by a special "movx" instruction. Up to 4 Kbytes of program instructions can be stored in the internal memory of the 8051, or the 8051 can be configured to use up to 64 Kbytes of external program memory The majority of the 8051's instructions are executed within 12 clock cycles.

Suppose we wanted to see if we can modify this 8051 core to consume less power. This first thing we would want to do is to measure the power the original core consumes executing a given program. If we were using Synopsys to obtain gate level power estimation we would perform the following steps:

Behavioral Synthesis and Simulation

1. Analyze each of the source files starting with the innermost entities.
2. Get your C code test program ready to simulate (i.e. converting your C file to VHDL ROM model)
3. We use the Synopsys VHDL Debugger to simulate the design, outputting a waveform to verify functionality is correct.
   
   
   
   
   
   

1. Now that we know this code works on the behavioral level, we synthesize the source code to gate level.
2. Now we analyze the gate files starting with the intermost entities.
3. We once again use the Synopsys VHDL Debugger to simulate the gate-level design, outputting a waveform to verify functionality is correct.

1. The toggle information that we collect will inform us of when each signal and net in our design chagnes form 1 to 0 or form 0 to 1. Since most power is consumed when a net switches, or toggles, we can then use this information to estimate the power of our design.
2. We create a file called run.scr which indicates how long the design needs to be simulated.
3. We can now simulate the design using vhdlsim The output of the simulation is a file containing the toggle information for every net in the design.
4. We convert the file using sim2dp command to obtain a file readable by dc_shell.

1. The actual power analysis will be performed using dc_shell.
2. After starting dc_shell, we read in our synthesized design.
3. If there is a clock in our design we must create a clock. The command works by creating a clock that will be used in power analysis. In the testbench of our design, we would have simulated a clock with a given frequency. Therefore, we will need to create a similar clock within dc_shell.
4. We will now use the information gathered from simulation by including the toggle file previously generated.
5. We are now ready to perform the actual power analysis. This is done with the "report_power -analysis_effort high" command.
6. At the end of the output from this command, dc_shell will report the power used by our design.

We have gone through high-level simplified steps required to obtain power of a design using Synopsys (For more detailed steps on synthesis and simulation you can refer to the dalton page). For the i8051 code, it takes only a couple of minutes to synthesize and simulate a behavioral level design. However, to synthesize the i8051 source code to gate level can take up to an hour. To simulate a gate level design can take anywhere from an hour to a week (sometimes more) depending on the code we are trying to simulate. The power analysis can take equally as long.