"Synopsys provides a full range of high-level design automation solutions for the design of integrated circuits, systems on a chip (SoCs) and electronic systems. By combining its expertise in high-level sysnthesis technology with its knowledge of silicion's physical effects, Synopsys employs system-level verification, RTL to GDSII closure and intellectual property solutions to help its customers get their silicon working quickly and accurately. Our products improve our customes' designs from virtually every vantage point, including performance, complexity, quality-of-results, cost power and time-to-market." -- Synopsys.com

The flow diagram (from Synopsys' website) depicts the areas in which Synopsys tools are capable of being involved :

So what does this mean to us? Basically, Synopsys provides a suite of tools to aid designers in the development and verification of circuits. Designers are able to specify the desired design at a high level, VHDL and Verilog, and Synopsys will synthesize this down to gate level. In addition there are tools designers can use along the way for verification, simulation, and power analysis.

Two Entity Implementations

In this lab, you will implement two different entities , MAX_1CMP and MAX_4CMP, which both calculate the maximum value of 8 inputs when the enable signal, enable, is high. Each input is a 4-bit number. The output, MaxValue, is the largest of the eight 4-bit inputs. In addition, the entitiy sets the output, Done, when the maximum value is computed indicating that the correct value is now on the output signal.

   max_val = 0;

   for( i=0 ; i<8 ; i++){
      max_val = max(max_val, input[i]);
   }

   output = max_val;
   

   max_val = 0;

   for( i=0; i<8; i++){
      max_val = max(max_val, input[i], input[i+1], input[i+2]);
   }

   output = max_val;
   

   type STATE_TYPE is ( S0, S1, .... ); 
   state : STATE_TYPE ;
   
   ...
   
   process( ... )
   begin
   
   if( rst = '1' ) then
      -- initialize stuff here

   elsif( clk'event and clk = '1' ) then
      case state is
         when S0 =>
            -- do stuff
         when S1 =>
        
   ...
 
      end case;
   end if;
   end process;