Introduction to Instruction Set Simulators

Lab 7: Introduction to Instruction Set Simulators

Introduction

An instruction set simulator reads in an executable program and simulates the execution of that program. Then based on the simulation, will output various information about the execution (e.g. address trace, cache performance, etc...).

Intel 8051 Simulator

The following is a high level simulator for the Intel 8051 written in C++. The simulator allows a user to simulate simple programs written for the 8051. The simulator provides statistics on instructions executed, instructions executed per second, execution cycles required by the 8051, and average instructions per second for an 8051 executing the same program. The following are not supported: input ports, interrupts, movx instructions.

Source Files

i8051.h
i8051.cc
main.cc
Makefile
8051sim.tar.gz (Contains all files)

Test Files

C HEX Size (byte) Simulation Time (ns) Signal Trace

negcnt.c negcnt.hex
39

270,000
P0 = 64, 65, 66, 67, 68, 69, 70, 71, 72, 73

gcd.c gcd.hex
51

327,000
P0 = 36, 25, 14, 3, 1

int2bin.c int2bin.hex
60

500,000
P0 = 0, 1, 0, 1, 0, 1, 0, 1

cast.c cast.hex
127

870,000
P0 = 01H, P1 = 23H, P2 = 45H, P3 = 67H

divmul.c divmul.hex
210

370,000
P0 = 10, 4, 134

fib.c fib.hex
305

1,042,000
P0 = 1, 1, 2, 3, 5, 8, 13, 21, 34, 55

sort.c sort.hex
544

3,600,000
P0 = 0, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19

sqroot.c sqroot.hex
1121

4,000,000
P0 = 9, P1 = 16, P2 = 25, P3 = 5

xram.c xram.hex
67

37,000,000
/I8051_XRM/XRAM(...) = 1, 2, 3, 4, ...

How to Use the Instruction Set Simulatior

Download files

Compile the files using the Makefile

Run simulator "8051sim <hexfile> <outputfile>"

Ctrl-C to exit (unless you specifiy exit condition)

Modes

To use the simulator, edit i8051.h and uncomment the PORTS, DEBUG, DEBUG_PC, and/or DETAIL macros to enable the respective output. Modify the macro PROGRAM_COMPLETION to the appropriate completion condition. If there is no program completion condition do not define PROGRAM_COMPLETION.

DEBUG

If defined, a trace of all instructions executed by the simulator will be outputted to the output file specified by the user.

DEBUG_PC

If defined and DEBUG is defined the PC for each instruction executed will be outputted to the output file.

PORTS

If defined, anytime one of the output ports of the 8051 changes all ports will be printed out.

PROGRAM COMPLETION

The simulator will continue executing the provided program until either the user hit Ctrl-C or the program completion condition is met. The program completion condition can be set by defining a macro PROGRAM_COMPLETION located in i8051.h to indicate the program completion condition, e.g., RAM[P0] == 0x01.

DETAIL

If defined, more information regarding each instruction will outputted to the output file.

SimpleScalar

SimpleScalar is a suite of tools consisting of a compiler, assembler, linker, and simulation environment for the SimpleScalar architecture. The SimpleScalar architecture is a superset of the MIPS architecture. SimpleScalar takes a binary compiled for the SimpleScalar architecute and simulates it's exeuction on one of the several procesor simulators provided.

Compilation

This has been taken care of for you. The corresponding output are the .out files.

Generating an Assembly File

log on to core "ssh -l yourlogin core.cs.ucr.edu"

run "objdump --disassemble file.out > outputfile" where file.out is one of the out file provided by the simplescalar tool and outputfile is the file containing the corresponding assembly

Generating a Trace File

log on to core "ssh -l yourlogin core.cs.ucr.edu"

run "sim-outorder -ptrace stdout : < file.out > | newTool < outputfile >" where file.out is one of the out file provided by the simplescalar tool and outputfile is the file containing the trace file

Simulators

Functional Simulator

NAME DESCRIPTION

sim-fast The fastest, least detailed simulator which does no time accounting, only functional simulation. It executes each instruction serially, simulating no instructions in parallel. It is optimized for raw speed, assumes no caches or instruction checking.

sim-safe This simulator also performs functional simulation, but checks for correct alignment and access permissions for each memory reference.

Cache Simulator

NAME DESCRIPTION

sim-cache Functional cache simulator. The simulator enables the user to specify various cache configurations and outputs the performacne of the cache.

sim-cheetah Functional cache simulator based on the Cheetah cache simulator. The Cheetah engine simulates multiple cache configurations with a single simulation. It also simulates fully associative caches efficently.

Profiler

NAME DESCRIPTION

sim-profile Functional simulator that produces profile information. It can generate detailed profiles on instruction classes and addresses, text symbols, memory accesses, branches, and data segment symbols.

To run any of the simulators:

log on to core "ssh -l yourlogin core.cs.ucr.edu"

executables are located at /home/codes2/simplescalar to run it "/home/codes2/simplescalar/<name of simulator> <*.out file>"

For more information on SimpleScalar and additional flags for various simulators you can refer to the Technical Report.

Lab Objective

You should try using both the 8051 simulator and simplescalar. This is your chance to familiarize yourself with these tools, so if you need to use them in later projects you'll have an advantage.

8051 Simulator

Try running the programs through the simulator

Try the different modes available.

See if you can generate a trace file.

See if you can generate an assembly file.

SimpleScalar

Try running the programs through the various simulators avaialable. Look at the outputs and see if you understand them.
For the cache simulator, try running the same program through the cache simulator and see what effect various cache configurations have.
See if you can generate a trace file.
See if you can generate an assembly file.

CS122B, Winter 2002

C	HEX	Size (byte)	Simulation Time (ns)	Signal Trace
negcnt.c	negcnt.hex	39	270,000	P0 = 64, 65, 66, 67, 68, 69, 70, 71, 72, 73
gcd.c	gcd.hex	51	327,000	P0 = 36, 25, 14, 3, 1
int2bin.c	int2bin.hex	60	500,000	P0 = 0, 1, 0, 1, 0, 1, 0, 1
cast.c	cast.hex	127	870,000	P0 = 01H, P1 = 23H, P2 = 45H, P3 = 67H
divmul.c	divmul.hex	210	370,000	P0 = 10, 4, 134
fib.c	fib.hex	305	1,042,000	P0 = 1, 1, 2, 3, 5, 8, 13, 21, 34, 55
sort.c	sort.hex	544	3,600,000	P0 = 0, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19
sqroot.c	sqroot.hex	1121	4,000,000	P0 = 9, P1 = 16, P2 = 25, P3 = 5
xram.c	xram.hex	67	37,000,000	/I8051_XRM/XRAM(...) = 1, 2, 3, 4, ...

Functional Simulator
NAME	DESCRIPTION
sim-fast	The fastest, least detailed simulator which does no time accounting, only functional simulation. It executes each instruction serially, simulating no instructions in parallel. It is optimized for raw speed, assumes no caches or instruction checking.
sim-safe	This simulator also performs functional simulation, but checks for correct alignment and access permissions for each memory reference.

Cache Simulator
NAME	DESCRIPTION
sim-cache	Functional cache simulator. The simulator enables the user to specify various cache configurations and outputs the performacne of the cache.
sim-cheetah	Functional cache simulator based on the Cheetah cache simulator. The Cheetah engine simulates multiple cache configurations with a single simulation. It also simulates fully associative caches efficently.

Profiler
NAME	DESCRIPTION
sim-profile	Functional simulator that produces profile information. It can generate detailed profiles on instruction classes and addresses, text symbols, memory accesses, branches, and data segment symbols.