Lab Times : MW 11-2
Room : SURGE 173
TA names : Jason Villarreal and Susan Cotterell
Email addresses : villarre@cs.ucr.edu and susanc@cs.ucr.edu
Groups up to two are allowed. No more than two people per group will be allowed. No exceptions (not even you)!
When designing embedded systems, it is essential to have a proper testing environment so that simulations can be run efficiently and the effects of modifications can be observed. Simulation environments are also important when giving demonstrations to potential buyers. If you can't show what your product will do, no one will pay you to build it.
For these reasons and more we are having you develop a small simulation environment in both VHDL and C and design and test out a product this lab.
You are to implement a controller for a traffic light as well as set up the simulation environment. The traffic light is a standard four way stop. Each direction has one left turn lane, a right turn lane, and a lane for going straight. Each direction has a left turn arrow and right turn arrow. The lights act just like they do in the real world, so there should never be a case when two cars can run into each other.
Each lane has a sensor that detects when a car has passed over it. This car will wait if the light is red or go through if the light is green. For the first lab you do not have to worry about yellow lights.
The lights should change depending on where cars are. If two or more cars arrive at the same time, the light favors changing. If no cars are present, the light will not change. The light starts off as a solid green in the north/south direction with red in all other directions. A right turn signal will be green whenever a right turn is safely possible without stopping (i.e. the cars to the right are capable of making a left turn). You do not need to worry about pedistrians, bicyclists, or stray dogs.
Describe the functionality of the light using a state machine and capture the state machine in VHDL using using the Aldec state capture tools (or code it up directly if you feel more comfortable doing so). By using the state machine capture tool you will be able to generate VHDL directly from your state diagram. Once you have the VHDL, simulate it by constructing a testbench and verifying correct behavior.
Code up both the state machine and the simulation environment in C++. Your code should use the same state machine model as the VHDL model, and output the state the lights are in for each tick of the clock.
The simulation environment will take a string consisting of tuples in the form of (time, lane). Each token is seperated by whitespace. The lanes are numbered as follows:
| 9 | 8 | 7 | | | | N
| < | v | > | | | | ^
----------------------------------------- |
| | | | | | | ^ 6
------ --- --- --- --- --- --- ----------
| | | | | | | < 5
------ --- --- --- --- --- --- ----------
| | | | | | | v 4
------ --- --- --- --- --- --- ----------
10 ^ | | | | | | |
------ --- --- --- --- --- --- ----------
11 > | | | | | | |
------ --- --- --- --- --- --- ----------
12 v | | | | | | |
------ --- --- --- --- --- --- ----------
| | | | < | ^ | > |
| | | | 1 | 2 | 3 |
For example, the string "( 1 , 2 ) ( 2 , 8 ) ( 5 , 10 )" signifies that at time 1 a car will arrive in lane 2 (the northbound center lane), at time 2 a car will arrive in lane 8 (the southbound center lane), and at time 5 a car will arrive in lane 10 (the eastbound left turn lane). You can assume that the input will be formatted correctly and that each time will be greater than or equal to the time before it (you cannot have more than one car in the same lane in one tick).
We will be testing your code with our own strings to verify functionality.