Homework 3
UCR CS122B Winter 2002
Prof. F. Vahid
Due Tuesday 2/26/02 at beginning of lecture

1. Cache-- Assume you have a processor with an 8-bit instruction
   address space, and a 16 row direct-mapped (1-way) cache. Assume
   a block size of 1. (Note: these numbers are for example purposes only 
   and do not reflect a real system). Assume the low-order address bits
   correspond to the index into the cache.

   (a) Precisely show how the 8-bit addresses would map to the 16 entry cache. 
   (b) Consider the following trace of instruction addresses:
       1,2,3,1,2,3,16,17,18,... (this pattern repeats 10 times in total).
       Show where these words would map to the cache. 
   (c) What would be the hit rate of this cache (% of time the word is in 
       the cache when accessed)?
   (d) Let's change the cache to an 8 row, 2-way set associative cache
       (note that this does not change the cache size). 
       Now show how the 8-bit addresses would map to the cache.
   (e) For the same trace as in (b), provide the mapping of the words
       to the cache, and give the hit rate.
   (f) Will using a 2-way set-associative cache always improve the 
       hit rate over a direct-mapped cache (for the same total size)? 
       Justify your answer -- provide a counterexample if necessary.

2. Loop cache-- Describe the basic idea and design of a loop cache, and
   discuss its benefits.

3. Core interfacing-- 
   (a) Draw the structure of a simple core that has one 
   internal register that can be read from a bus using memory-mapped I/O. 
   Assume a simple four-phase handshake protocol. Give the timing 
   diagram for a register access.
   (b) Discuss why bus wrappers are useful for cores.
   (c) Draw the structure of a core with a bus wrapper, with the wrapper
   and the core internals communicating with a separate handshake protocol,
   and give a timing diagram. Compare the register read latency with part (a).
   (d) Highlight a method to eliminate this latency, assuming the value
   in the bus wrapper can be up to four cycles old. 

4. Experiment with the oven controller simulator at
   http://newton.ex.ac.uk/teaching/CDHW/Feedback/  (see the Oven Simulator).
   (a) Create a P-only controller by setting the D and I values to 0.
       Examine P values ranging from 1 to 100,000.
       Describe the controller's behavior for different ranges of P.
       Provide a printout for the "best" P, including your definition of best.
   (b) Create a PD controller, using P = 1000.
       Describe the controller's behavior for different ranges of D.
       Provide a printout for the "best" D, including your definition of best.
   (c) Create a PI controller, using P = 1000.
       Describe the controller's behavior for different ranges of I.
       Provide a printout for the "best" I, including your definition of best.
   (d) Create a PID controller. Try to use the approach described in the
       article handed out in class to obtain values for P, I and D.
       Did the approach in class work?  Can you improve those values?
       Provide a printout for the "best" PID controller you can obtain, and
       compare with your earlier versions of P, PD, and PI controllers.
   (e) Run an ON/OFF controller simulation, and compare the results
       with the PID controller. Explain what an on/off controller is.
   (General suggestion: I suggest you click on the table-of-contents link
   of the URL and read the overview -- it's an excellent summary of
   control!)