--
-- Tony Givargis
--

--**************************************************************************--

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.all;

--**************************************************************************--

entity WRLED is 
	port(val : in UNSIGNED (3 downto 0);
	     led : out STD_LOGIC_VECTOR (6 downto 0));
end WRLED;

--**************************************************************************--

architecture WRLED_ARCH of WRLED is
begin
	process(val)
	begin
		case val is
			when "0000" => led <= "1110111";
			
                        -- fill in the other cases                         
                        -- a "1" will turn on the corresponding segment    
                        -- so "1110111" turns on segments a, b, c, e, f, g 
                        -- creating a zero on the 7-segment display        

			when others => led <= "0001000";
		end case;
	end process;
end WRLED_ARCH;