library IEEE;
use IEEE.std_logic_1164.all;  
use IEEE.STD_LOGIC_ARITH.all;

entity DivideBy12 is
	port( clk: in std_logic;
	newclk: out std_logic
	);
end DivideBy12;

architecture beh of DivideBy12 is
signal temp: unsigned (0 to 3):= "0000";
begin	  
	process(clk)
	begin
		if( clk'event and clk='1' ) then

		case temp is
			when "1100" =>
				newclk <= '1';
				temp <= "0000";
			when others =>
				newclk <= '0';
				temp <= temp + "0001";
		end case;
		end if;
	end process;
end beh;

library IEEE;
use IEEE.std_logic_1164.all;  
use IEEE.STD_LOGIC_ARITH.all;

entity Counting is
	port (TCONin: in unsigned(7 downto 0);
	TMOD: in unsigned(7 downto 0);
	INT0: in std_logic;
	output: out std_logic
	);
end Counting;

architecture beh of Counting is
begin	   
	process (TCONin, TMOD, INT0)
	begin		
		if ((STD_LOGIC_VECTOR(TCONin) and "00010000") = "00000000") then
			output <= '0';
		elsif (((STD_LOGIC_VECTOR(TMOD) and "00001000") = "00001000") or INT0 = '1') then
			output <= '1';
		else
			output <= '0';
		end if;
	end process;
end beh;
		
library IEEE;
use IEEE.std_logic_1164.all;  
use IEEE.STD_LOGIC_ARITH.all;

entity register8bit is
	port( clk: in std_logic;
	input: in std_logic;
	reset: in std_logic;
	clear: in std_logic;
	output: out unsigned(7 downto 0);
	carry: out std_logic
	);
end register8bit;

architecture beh of register8bit is
begin
	process(clk, reset)
	variable temp: unsigned(7 downto 0);
	begin
		if (reset = '1') then
			temp := "00000000";
			output <= "00000000";
			carry <= '0';
		elsif (clk'event and clk='1') then
			if( clear = '1' ) then
				temp := "00000000";
				output <= "00000000";
				carry <= '0';
			elsif (input = '1') then
				case temp is
					when "11111111" =>
						carry <= '1';
						temp := "00000000";
						output <= "00000000";
					when others =>
						temp := temp + "00000001";
						output <= temp;
						carry <= '0';
				end case;
			end if;
		end if;
	end process;
end beh;					

library IEEE;
use IEEE.std_logic_1164.all;  
use IEEE.STD_LOGIC_ARITH.all;

entity Control is
	port( newclock: in std_logic;
	Time0: in std_logic;
	input: in std_logic;
	TMODin: in unsigned (7 downto 0);
	output:out std_logic
	);						
end Control;

architecture beh of Control is
begin
	process (newclock, Time0, input)
	variable TMODtemp: STD_LOGIC_VECTOR(7 downto 0);
	begin  
		TMODtemp:= STD_LOGIC_VECTOR(TMODin) and "00000100"; 
		if (input = '1') then
			case TMODtemp is
				when "00000000" =>
					output <= Time0;
				when others =>
					output <= newclock;
			end case;
		else
			output <= '0';
		end if;
	end process;
end beh;		  			  

library IEEE;
use IEEE.std_logic_1164.all;  
use IEEE.STD_LOGIC_ARITH.all;

entity InterruptProcess is
	port (rst: in std_logic;
	TCONin: in unsigned (7 downto 0);
	TL1: in unsigned (7 downto 0);
	TH1: in unsigned (7 downto 0);
	reset: out std_logic;
	TCONout: out unsigned (7 downto 0)
	);
end InterruptProcess;

architecture beh of InterruptProcess is
begin
	process (rst, TL1, TH1)	
	variable temp: std_logic_vector (7 downto 0);
	begin
		if (rst = '1') then
			TCONout <= TCONin;
			reset <= '1';
		elsif (std_logic_vector(TL1) = "00011111") then
			if (std_logic_vector(TH1) = "11111111") then
				temp := std_logic_vector(TCONin) or "00100000";
				TCONout <= unsigned(temp);
				reset <= '1';
			else
				TCONout <= TCONin;
				reset <= '0';
			end if;
		else
			TCONout <= TCONin;
			reset <= '0';
		end if;
	end process;
end beh;


library IEEE;
use IEEE.std_logic_1164.all;  
use IEEE.STD_LOGIC_ARITH.all;

entity Timer is
	port (
		TMOD: in unsigned(7 downto 0);
		TCONin: in unsigned(7 downto 0);
		Timer0Pin: in std_logic;
		clk: in std_logic;
		INT0Pin: in std_logic;
		rst: in std_logic;
		TCONout: out unsigned (7 downto 0)
	);
end Timer;	 

architecture struct of Timer is

component DivideBy12
	port( clk: in std_logic;
	newclk: out std_logic
	);			   
end component;

component Counting
	port (TCONin: in unsigned(7 downto 0);
	TMOD: in unsigned(7 downto 0);
	INT0: in std_logic;
	output: out std_logic
	);			  
end component;

component register8bit
	port(clk: in std_logic; 
	input: in std_logic;
	reset: in std_logic;
	clear: in std_logic;
	output: out unsigned(7 downto 0);
	carry: out std_logic
	);
end component;	

component Control
	port( newclock: in std_logic;
	Time0: in std_logic;
	input: in std_logic;
	TMODin: in unsigned (7 downto 0);
	output:out std_logic
	);				
end component; 

component InterruptProcess
	port (rst: in std_logic;
	TCONin: in unsigned (7 downto 0);
	TL1: in unsigned (7 downto 0);
	TH1: in unsigned (7 downto 0);
	reset: out std_logic;
	TCONout: out unsigned (7 downto 0)
	);
end component;

signal a: std_logic;
signal b: std_logic;
signal c: std_logic;
signal d: std_logic;
signal e: unsigned (7 downto 0);
signal f: UNSIGNED (7 downto 0);
signal g: std_logic;
signal h: std_logic;

begin		 
U1: DivideBy12 port map (clk, a);
U2: Counting port map (TCONin, TMOD, INT0Pin, b);
U3: Control port map (a, Timer0Pin, b, TMOD, c);
TH1: register8bit port map (clk, c, rst, h, f, d);
TL1: register8bit port map (clk, d, rst, h, e, g);
U6: InterruptProcess port map (rst, TCONin, e, f, h, TCONout);

end struct;