CS122A
Fall Quarter, 1999
Lab 7 -- VHDL: Designing A Calculator And Downloading It Onto
An XS40 Board
Prof. Frank Vahid
Purpose
The purpose of this lab is to implement a finite state machine in VHDL to
perform simple calculations like addition, subtraction, and multiplication.
Write a testbench to check it's functionality. Then download it onto an
XS40 board using DIP switches to vary the inputs.
Assignment
In this lab:
Apparatus Required:
Schematic:

Program:
--
-- Tony Givargis
--
--********************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
--********************************************************************
entity XS40 is
port (rst: in STD_LOGIC;
clk: in STD_LOGIC;
--define operands and operator here
led: out UNSIGNED(6 downto 0));
end XS40;
--********************************************************************
architecture XS40_ARCH of XS40 is
component WRLED
port(val: in UNSIGNED(3 downto 0);
led: out UNSIGNED(6 downto 0));
end component;
signal val:UNSIGNED(3 downto 0);
begin
U1:WRLED port map(val, led);
process(rst, clk, ...)
-- insert calculator code here
end process;
end XS40_ARCH;
Steps to be followed:
Conclusion:
(Note: Jumper on J4 needs to be set when loading program
but disconnected when running program)
Show the TA the waveforms from the ALDEC VHDL simulation and
demonstrate your implementations on the XS40 board to the TA.
Please include your VHDL source files while turning in the report.